ADAV801ASTZ Analog Devices Inc, ADAV801ASTZ Datasheet - Page 35

• Manufacturer Part Number: ADAV801ASTZ
• Description: IC CODEC AUDIO R-DVD 3.3V 64LQFP
• Manufacturer: Analog Devices Inc
• Type: Audio Codecr

Specifications of ADAV801ASTZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 102 / 101
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 2
• No. Of Output Channels: 2
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 102dB
• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: LQFP
• Adc/dac Resolution: 24b
• Interface Type: Serial (SPI)
• Mounting: Surface Mount
• Number Of Adc's: 2
• Number Of Dac's: 2
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 64
• Power Supply Type: Analog/Digital
• Sample Rate: 96KSPS
• Screening Level: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADAV801EBZ - BOARD EVALUATION FOR ADAV801
• Lead Free Status / Rohs Status: Compliant

Receiver Configuration 2—Address 0001010 (0x0A)
Table 33. Receiver Configuration 2 Register Bit Map
7
RxMUTE
Table 34. Receiver Configuration 2 Register Bit Descriptions
Bit Name
RxMUTE
SP_PLL
SP_PLL_SEL[1:0]
NO NONAUDIO
NO_VALIDITY
6
SP_PLL
Description
Hard-mutes the audio output for the AES3/S/PDIF receiver.
AES3/S/PDIF receiver PLL accepts a left/right clock from one of the four serial ports as the PLL reference clock.
Selects one of the four serial ports as the reference clock to the PLL when SP_PLL is set.
When the NO NONAUDIO bit is set, data from the AES3/S/PDIF receiver is not allowed into the sample rate converter
(SRC). If the NO NONAUDIO data is due to DTS, AAC, and so on, as defined by the IEC61937 standard, then the data
from the AES3/S/PDIF receiver is not allowed into the SRC regardless of the state of this bit.
When the NO_VALIDITY bit is set, data from the AES3/S/PDIF receiver is not allowed into the SRC.
0 = AES3/S/PDIF receiver is not muted.
1 = AES3/S/PDIF receiver is muted.
0 = Left/right clock generated from the AES3/S/PDIF preambles is the reference clock to the PLL.
1 = Left/right clock from one of the serial ports is the reference clock to the PLL.
00 = Playback port is selected.
01 = Auxiliary input port is selected.
10 = Record port is selected.
11 = Auxiliary output port is selected.
0 = AES3/S/PDIF receiver data is sent to the SRC.
1 = Data from the AES3/S/PDIF receiver is not allowed into the SRC, if the NO NONAUDIO bit is set.
0 = AES3/S/PDIF receiver data is sent to the SRC.
1 = Data from the AES3/S/PDIF receiver is not allowed into the SRC, if the NO_VALIDITY bit is set.
5
SP_PLL_ SEL1
4
SP_PLL_ SEL0
Rev. A | Page 35 of 60
3
Reserved
2
Reserved
1
NO NONAUDIO
0
NO_VALIDITY
ADAV801