ADAV801ASTZ Analog Devices Inc, ADAV801ASTZ Datasheet - Page 41

• Manufacturer Part Number: ADAV801ASTZ
• Description: IC CODEC AUDIO R-DVD 3.3V 64LQFP
• Manufacturer: Analog Devices Inc
• Type: Audio Codecr

Specifications of ADAV801ASTZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 102 / 101
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 2
• No. Of Output Channels: 2
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 102dB
• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: LQFP
• Adc/dac Resolution: 24b
• Interface Type: Serial (SPI)
• Mounting: Surface Mount
• Number Of Adc's: 2
• Number Of Dac's: 2
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 64
• Power Supply Type: Analog/Digital
• Sample Rate: 96KSPS
• Screening Level: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADAV801EBZ - BOARD EVALUATION FOR ADAV801
• Lead Free Status / Rohs Status: Compliant

Sample Rate Converter Error—Address 0011010 (0x1A)
Table 65. Sample Rate Converter Error Register (Read-Only) Bit Map
7
Reserved
Table 66. Sample Rate Converter Error Register (Read-Only) Bit Descriptions
Bit Name
TOO_SLOW
OVRL
OVRR
MUTE_IND
Sample Rate Converter Error Mask—Address 0011011 (0x1B)
Table 67. Sample Rate Converter Error Mask Register Bit Map
7
Reserved
Table 68. Sample Rate Converter Error Mask Register Bit Descriptions
Bit Name
OVRL Mask
OVRR Mask
MUTE_IND MASK
6
Reserved
6
Reserved
Description
This bit is set when the clock to the SRC is too slow, that is, there are not enough clock cycles to complete the
internal convolution.
This bit is set when the left output data of the sample rate converter has gone over the full-scale range and has been
clipped. This bit is not cleared until the register is read.
This bit is set when the right output data of the sample rate converter has gone over the full-scale range and has
been clipped. This bit is not cleared until the register is read.
Mute indicated. This bit is set when the SRC is in fast mode and clicks or pops can be heard in the SRC output data.
The output of the SRC can be muted, if required, until the SRC is in slow mode. Once read, this bit remains in its state
and does not generate an interrupt until it has changed state.
Description
Masks the OVRL from generating an interrupt.
Masks the OVRR from generating an interrupt.
Masks the MUTE_IND from generating an interrupt.
0 = OVRL bit does not generate an interrupt.
1 = OVRL bit generates an interrupt.
0 = OVRR bit does not generate an interrupt.
1 = OVRR bit generates an interrupt. Reserved.
0 = MUTE_IND bit does not generate an interrupt.
1 = MUTE_IND bit generates an interrupt.
5
Reserved
5
Reserved
4
Reserved
4
Reserved
Rev. A | Page 41 of 60
3
Reserved
3
TOO_SLOW
2
OVRL Mask
2
OVRL
1
OVRR Mask
1
OVRR
0
MUTE_IND MASK
0
MUTE_IND
ADAV801