ADAV801ASTZ Analog Devices Inc, ADAV801ASTZ Datasheet - Page 52

• Manufacturer Part Number: ADAV801ASTZ
• Description: IC CODEC AUDIO R-DVD 3.3V 64LQFP
• Manufacturer: Analog Devices Inc
• Type: Audio Codecr

Specifications of ADAV801ASTZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 102 / 101
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 2
• No. Of Output Channels: 2
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 102dB
• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: LQFP
• Adc/dac Resolution: 24b
• Interface Type: Serial (SPI)
• Mounting: Surface Mount
• Number Of Adc's: 2
• Number Of Dac's: 2
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 64
• Power Supply Type: Analog/Digital
• Sample Rate: 96KSPS
• Screening Level: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADAV801EBZ - BOARD EVALUATION FOR ADAV801
• Lead Free Status / Rohs Status: Compliant

ADAV801
PLL Control Register 1—Address 1110100 (0x74)
Table 128. PLL Control Register 1 Bit Map
7
DIRIN_CLK1
Table 129. PLL Control Register 1 Bit Descriptions
Bit Name
DIRIN_CLK[1:0]
MCLKODIV
PLLDIV
PLL2PD
PLL1PD
XTLPD
SYSCLK3
6
DIRIN_CLK0
Description
Recovered S/PDIF clock sent to SYSCLK3.
Divide input MCLK by 2 to generate MCLKO.
Divide XIN by 2 to generate the PLL master clock.
Power-down PLL2.
Power-down PLL1.
Power-down XTAL oscillator.
Clock output for SYSCLK3.
00 = SYSCLK3 comes from PLL block.
01 = Reserved.
10 = Reserved.
11 = SYSCLK3 is the recovered S/PDIF clock from DIRIN.
0 = Disabled.
1 = Enabled.
0 = Disabled.
1 = Enabled.
0 = Normal.
1 = Power-down.
0 = Normal.
1 = Power-down.
0 = Normal.
1 = Power-down.
0 = 512 × f
1 = 256 × f
5
MCLKODIV
S
S
.
.
4
PLLDIV
Rev. A | Page 52 of 60
3
PLL2PD
2
PLL1PD
1
XTLPD
0
SYSCLK3