ADAV801ASTZ Analog Devices Inc, ADAV801ASTZ Datasheet - Page 34

• Manufacturer Part Number: ADAV801ASTZ
• Description: IC CODEC AUDIO R-DVD 3.3V 64LQFP
• Manufacturer: Analog Devices Inc
• Type: Audio Codecr

Specifications of ADAV801ASTZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 102 / 101
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 2
• No. Of Output Channels: 2
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 102dB
• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: LQFP
• Adc/dac Resolution: 24b
• Interface Type: Serial (SPI)
• Mounting: Surface Mount
• Number Of Adc's: 2
• Number Of Dac's: 2
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 64
• Power Supply Type: Analog/Digital
• Sample Rate: 96KSPS
• Screening Level: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADAV801EBZ - BOARD EVALUATION FOR ADAV801
• Lead Free Status / Rohs Status: Compliant

ADAV801
Group Delay and Mute—Address 0001000 (0x08)
Table 29. Group Delay and Mute Register Bit Map
7
MUTE_SRC
Table 30. Group Delay and Mute Register Bit Descriptions
Bit Name
MUTE_SRC
GRPDLY[6:0]
Receiver Configuration 1—Address 0001001 (0x09)
Table 31. Receiver Configuration 1 Register Bit Map
7
NOCLOCK
Table 32. Receiver Configuration 1 Register Bit Descriptions
Bit Name
NOCLOCK
RxCLK[1:0]
AUTO_DEEMPH
ERR[1:0]
LOCK[1:0]
6
RxCLK1
6
GRPDLY6
Description
Selects the source of the receiver clock when the PLL is not locked.
Determines the oversampling ratio of the recovered receiver clock.
Automatically de-emphasizes the data from the receiver based on the channel status information.
Defines what action the receiver should take, if the receiver detects a parity or biphase error.
Defines what action the receiver should take, if the PLL loses lock.
0 = Recovered PLL clock is used.
1 = ICLK1 is used.
00 = RxCLK is a 128 × f
01 = RxCLK is a 256 × f
10 = RxCLK is a 512 × f
11 = Reserved.
0 = Automatic de-emphasis is disabled.
1 = Automatic de-emphasis is enabled.
00 = No action is taken.
01 = Last valid sample is held.
10 = Invalid sample is replaced with zeros.
11 = Reserved.
00 = No action is taken.
01 = Last valid sample is held.
10 = Zeros are sent out after the last valid sample.
11 = Soft-mute of the last valid audio sample.
Soft-mutes the output of the sample rate converter.
Description
Adds delay to the sample rate converter FIR filter by GRPDLY[6:0] input samples.
0 = No mute.
1 = Soft mute.
0000000 = No delay.
0000001 = 1 sample delay.
0000010 = 2 sample delay.
1111110 = 126 sample delay.
1111111 = 127 sample delay.
5
RxCLK0
5
GRPDLY5
S
S
S
recovered clock.
recovered clock.
recovered clock.
4
AUTO_DEEMPH
4
GRPDLY4
Rev. A | Page 34 of 60
3
GRPDLY3
3
ERR1
2
GRPDLY2
2
ERR0
1
GRPDLY1
1
LOCK1
0
GRPDLY0
0
LOCK0