ADAV801ASTZ Analog Devices Inc, ADAV801ASTZ Datasheet - Page 54

• Manufacturer Part Number: ADAV801ASTZ
• Description: IC CODEC AUDIO R-DVD 3.3V 64LQFP
• Manufacturer: Analog Devices Inc
• Type: Audio Codecr

Specifications of ADAV801ASTZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 102 / 101
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 2
• No. Of Output Channels: 2
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 102dB
• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: LQFP
• Adc/dac Resolution: 24b
• Interface Type: Serial (SPI)
• Mounting: Surface Mount
• Number Of Adc's: 2
• Number Of Dac's: 2
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 64
• Power Supply Type: Analog/Digital
• Sample Rate: 96KSPS
• Screening Level: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADAV801EBZ - BOARD EVALUATION FOR ADAV801
• Lead Free Status / Rohs Status: Compliant

ADAV801
Internal Clocking Control Register 1—Address 1110110 (0x76)
Table 132. Internal Clocking Control Register 1 Bit Map
7
DCLK2
Table 133. Internal Clocking Control Register 1 Bit Descriptions
Bit Name
DCLK[2:0]
ACLK[2:0]
ICLK2_[1:0]
Internal Clocking Control Register 2—Address 1110111 (0x77)
Table 134. Internal Clocking Control Register 2 Bit Map
7
Reserved
Table 135. Internal Clocking Control Register 2 Bit Descriptions
Bit Name
ICLK1_[1:0]
PLL2INT[1:0]
PLL1INT
6
DCLK1
6
Reserved
Description
DAC clock source select.
ADC clock source select.
Source selector for internal clock ICLK2.
Description
Source selector for internal clock ICLK1.
PLL2 internal selector (see Figure 38).
PLL1 internal selector.
000 = XIN.
001 = MCLKI.
010 = PLLINT1.
011 = PLLINT2.
100 = DIR PLL (512 × f
101 = DIR PLL (256 × f
110 = XIN.
111 = XIN.
000 = XIN.
001 = MCLKI.
010 = PLLINT1.
011 = PLLINT2.
100 = DIR PLL (512 × f
101 = DIR PLL (256 × f
110 = XIN.
111 = XIN.
00 = XIN.
01 = MCLKI.
10 = PLLINT1.
11 = PLLINT2.
00 = XIN.
01 = MCLKI.
10 = PLLINT1.
11 = PLLINT2.
00 = FS2.
01 = FS2/2.
10 = FS3.
11 = FS3/2.
0 = FS1.
1 = FS1/2.
5
DCLK0
5
Reserved
S
S
S
S
).
).
).
).
4
ACLK2
4
ICLK1_1
Rev. A | Page 54 of 60
3
ACLK1
3
ICLK1_0
2
ACLK0
2
PLL2INT1
1
1
ICLK2_1
PLL2INT0
0
ICLK2_0
0
PLL1INT