TDA8007BHL/C3,118 NXP Semiconductors, TDA8007BHL/C3,118 Datasheet - Page 24

• Manufacturer Part Number: TDA8007BHL/C3,118
• Description: IC INTERFACE CARD MP 48-LQFP
• Manufacturer: NXP Semiconductors

Specifications of TDA8007BHL/C3,118

• Controller Type: Multiprotocol IC Card Interface
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 6 V
• Current - Supply: 315mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3520-2; 935272525118; TDA8007BHLBE-T

NXP Semiconductors
TDA8007BHL
Product data sheet
8.2.3.1 Programmable Divider Register (PDR)
8.2.3.2 UART Configuration Registers (UCR) 2
8.2.3 Card registers
When cards 1, 2 or 3 are selected, the following registers may be used for programming
some specific parameters.
The programmable divider registers PDR1, PDR2 and PDR3 are used for counting the
cards clock cycles forming the ETU (see
These are auto-reload 8-bit counters.
Table 21.
[1]
The UART configuration registers 2 UCR12, UCR22 and UCR32, relate the UART
configuration.
Table 22.
[1]
Table 23.
UC27
Bit
7
6
5
Fig 16. Block diagram
PD7
7
Register value at reset: all bits are cleared after reset.
Register value at reset: all bits are cleared after reset.
7
DISTBE/RBF DISAUX
Symbol
UC27
DISTBE/RBF
DISAUX
Register PDR1,PRDR2, PDR3 (address 02h; read and write)
Register UCR1,UCR2, UCR3 (address 03h; read and write)
Description of UCR2 bits
bit CKU
2f
PD6
6
f
All information provided in this document is subject to legal disclaimers.
CLK
CLK
6
Rev. 8 — 11 January 2011
MULTIPLEXER
Description
not used
disable TBE/RBF interrupt bit. If bit DISTBE/RBF = 1, then reception
or transmission of a character will not generate an interrupt. This
feature is useful for increasing communication speed with the card; in
this case, a copy of the bit TBE/RBF within register MSR must be
polled (and not the original) in order not to lose priority interrupts which
can occur in register USR.
disable auxiliary interrupt. If bit DISAUX in register UCR2 is set, then
a change on pin INTAUX will not generate an interrupt, but bit INTAUXL
will be set. Therefore, it is necessary to read register HSR before
bit DISAUX is to be reset to avoid an interrupt by bit INTAUXL. In order
to avoid an interrupt during a change of card, it is better to set
bit DISAUX in register UCR2 for all cards.
PD5
5
5
PDWN
PD4
4
4
PRESCALER
(31 or 32)
Figure
SAN
16).
PD3
3
3
PROGRAMMABLE
AUTOCONV CKU
Multiprotocol IC card interface
REGISTER
(1 to 256)
DIVIDER
PD2
2
TDA8007BHL
2
[1]
PD1
© NXP B.V. 2011. All rights reserved.
1
fce905
ETU
1
PSC
PD0
24 of 51
0
0