KSZ8873MLL Micrel Inc, KSZ8873MLL Datasheet - Page 12

• Manufacturer Part Number: KSZ8873MLL
• Description: IC ETHERNET SWITCH 3PORT 64-LQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8873MLL

• Data Rate: 100Mbps
• Controller Type: Ethernet Switch Controller
• Interface: MII
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• No. Of Ports: 3
• Ethernet Type: IEEE 802.3u
• Supply Current: 115mA
• Supply Voltage Range: 2.5V, 3.3V
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Svhc: No SVHC (15-Dec-2010)
• Base: RoHS Compliant
• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Fiber Support: No
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog/Digital
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 1.89/3.465V
• Operating Temperature Classification: Commercial
• Interface Type: MII, RMII
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-3459

Micrel, Inc.
September 2010
Pin Number
28
29
30
31
32
33
34
35
36
37
38
39
40
SMRXD32
SMRXD31
SCRS3/
SCOL3/
SMRXC3/
SPIQ
SPISN
Pin Name
SMRXDV3
SMRXD33/
REFCLKO_3
GND
SMRXD30
NC
NC
NC
GND
VDDC
Type
lpu/O
lpu/O
Ipu/O
Ipu/O
Gnd
lpu/O
I/O
I/O
I/O
Gnd
P
lpu/O
I
(1)
Description
Switch MII receive data valid
Strap option: MII mode selection
PU = PHY mode.
PD = MAC mode (In MAC mode, port 3 has to be connected an external
PHY for the normal operation)
MLL/FLL: Switch MII receive data bit 3/
RLL: Output reference clock in RMII mode.
Strap option: enable auto-negotiation on port 2 (P2ANEN)
PU = enable P2ANEN
PD = disable P2ANEN
Switch MII/RMII receive data bit 2
Strap option: Force the speed on port 2
PU = force port 2 to 100BT if P2ANEN = 0
PD = force port 2 to 10BT if P2ANEN = 0
Switch MII/RMII receive data bit 1
Strap option: Force duplex mode (P2DPX)
PU = port 2 default to full duplex mode if P2ANEN = 1 and auto-
negotiation fails. Force port 2 in full duplex mode if P2ANEN = 0.
PD = Port 2 set to half duplex mode if P2ANEN = 1 and auto-negotiation
fails. Force port 2 in half duplex mode if P2ANEN = 0.
Digital ground
Switch MII receive data bit 0
Strap option: Force flow control on port 2 (P2FFC)
PU = always enable (force) port 2 flow control feature, regardless of Auto-
Negotiation result.
PD = port 2 flow control is enabled by auto- negotiation result.
MLL/FLL: Switch MII carrier sense
RLL: No connection, Internal pull up.
MLL/FLL: Switch MII collision detect
RLL: No connection, Internal pull up.
MLL/FLL: Switch MII receive clock.
Output in PHY MII mode
Input in MAC MII mode
RLL: No Connection.
Digital ground
SPI slave mode: serial data output
Note: an external pull-up is needed on this pin when it is in use.
Strap option: XCLK Frequency Selection
PU = 25 MHz
PD = 50 MHz
When SPISN is high, the KSZ8873MLL/FLL/RLL is deselected and SPIQ
is held in high impedance state.
A high-to-low transition is used to initiate SPI data transfer.
Note: an external pull-up is needed on this pin when it is in use.
1.8V digital core power input from VDDCO (pin 56).
SPI slave mode: chip select (active low)
12
KSZ8873MLL/FLL/RLL
M9999-092309-1.2