KSZ8873MLL Micrel Inc, KSZ8873MLL Datasheet - Page 23
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KSZ8873MLL
Manufacturer Part Number
KSZ8873MLL
Description
IC ETHERNET SWITCH 3PORT 64-LQFP
Manufacturer
Micrel Inc
Specifications of KSZ8873MLL
Data Rate
100Mbps
Controller Type
Ethernet Switch Controller
Interface
MII
Voltage - Supply
1.8V, 2.5V, 3.3V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
No. Of Ports
3
Ethernet Type
IEEE 802.3u
Supply Current
115mA
Supply Voltage Range
2.5V, 3.3V
Digital Ic Case Style
LQFP
No. Of Pins
64
Svhc
No SVHC (15-Dec-2010)
Base
RoHS Compliant
Number Of Primary Switch Ports
3
Internal Memory Buffer Size
32
Fiber Support
No
Integrated Led Drivers
Yes
Phy/transceiver Interface
MII
Power Supply Type
Analog/Digital
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
1.89/3.465V
Operating Temperature Classification
Commercial
Interface Type
MII, RMII
Operating Temperature Range
0°C To +70°C
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
576-3459
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
KSZ8873MLL
Manufacturer:
Micrel Inc
Quantity:
1 934
Company:
Part Number:
KSZ8873MLL
Manufacturer:
ADI
Quantity:
27
Company:
Part Number:
KSZ8873MLL AM
Manufacturer:
Micrel
Quantity:
1 638
Company:
Part Number:
KSZ8873MLLJ
Manufacturer:
Micrel
Quantity:
323
Micrel, Inc.
Normal Operation Mode
This is the default setting bit[1:0]=00 in register 195 after the chip power-up or hardware reset . When
KSZ8873MLL/FLL/RLL is in this normal operation mode, all PLL clocks are running, PHY and MAC are on and the host
interface is ready for CPU read or write.
During the normal operation mode, the host CPU can set the bit[1:0] in register 195 to transit the current normal operation
mode to any one of the other three power management operation modes.
Energy Detect Mode
The energy detect mode provides a mechanism to save more power than in the normal operation mode when the
KSZ8873MLL/FLL/RLL is not connected to an active link partner. In this mode, the device will save up to 50% of the
power. If the cable is not plugged, the KSZ8873MLL/FLL/RLL can automatically enter to a low power state, a.k.a., the
energy detect mode. In this mode, KSZ8873MLL/FLL/RLL will keep transmitting 120ns width pulses at 1 pulse/s rate.
Once activity resumes due to plugging a cable or attempting by the far end to establish link, the KSZ8873MLL/FLL/RLL
can automatically power up to normal power state in energy detect mode.
Energy detect mode consists of two states, normal power state and low power state. While in low power state, the
KSZ8873MLL/FLL/RLL reduces power consumption by disabling all circuitry except the energy detect circuitry of the
receiver. The energy detect mode is entered by setting bit[1:0]=01 in register 195. When the KSZ8873MLL/FLL/RLL is in
this mode, it will monitor the cable energy. If there is no energy on the cable for a time longer than pre-configured value at
bit[7:0] Go-Sleep time in register 196, KSZ8873MLL/FLL/RLL will go into a low power state. When KSZ8873MLL/FLL/RLL
is in low power state, it will keep monitoring the cable energy. Once the energy is detected from the cable,
KSZ8873MLL/FLL/RLL will enter normal power state. When KSZ8873MLL/FLL/RLL is at normal power state, it is able to
transmit or receive packet from the cable.
It will save about 87% of the power when MII interface is in PHY mode, pin SMTXER3/MII_LINK_3 is connected to High,
register 195 bit [1:0] =01, bit 2 =1(Disable PLL), not cables are connected.
Soft Power Down Mode
The soft power down mode is entered by setting bit[1:0]=10 in register 195. When KSZ8873MLL/FLL/RLL is in this mode,
all PLL clocks are disabled, the PHY and the MAC are off, all internal registers value will not change. When the host set
bit[1:0]=00 in register 195, this device will be back from current soft power down mode to normal operation mode
Power Saving Mode
The power saving mode is entered when auto-negotiation mode is enabled, cable is disconnected, and by setting
bit[1:0]=11 in register 195. When KSZ8873MLL/FLL/RLL is in this mode, all PLL clocks are enabled, MAC is on, all
internal registers value will not change, and host interface is ready for CPU read or write. In this mode, it mainly controls
the PHY transceiver on or off based on line status to achieve power saving. The PHY remains transmitting and only turns
off the unused receiver block. Once activity resumes due to plugging a cable or attempting by the far end to establish link,
the KSZ8873MLL/FLL/RLL can automatically enabled the PHY power up to normal power state from power saving mode.
During this power saving mode, the host CPU can set bit[1:0] =0 in register 195 to transit the current power saving mode
to any one of the other three power management operation modes.
Port based Power Down Mode
In addition, the KSZ8873MLL/FLL/RLL features a per-port power down mode. To save power, a PHY port that is not in
use can be powered down via port control register 29 or 45 bit 3, or MIIM PHY register. It will saves about 15mA per port.
September 2010
KSZ8873MLL/FLL/RLL
Internal PLL Clock
Tx/Rx PHY
MAC
Host Interface
Function Blocks
Enabled
Enabled
Enabled
Enabled
Normal Mode
Enabled
Rx unused block disabled Energy detect at Rx
Enabled
Enabled
Power Saving Mode
Table 3. Internal Function Block Status
Power Management Operation Modes
23
Disabled
Disabled
Disabled
Energy Detect Mode
Disabled
Disabled
Disabled
Disabled
Soft Power Down Mode
KSZ8873MLL/FLL/RLL
M9999-092309-1.2