KSZ8873MLL Micrel Inc, KSZ8873MLL Datasheet - Page 36
![IC ETHERNET SWITCH 3PORT 64-LQFP](/photos/6/81/68149/64-lqfp-micrel_sml.jpg)
KSZ8873MLL
Manufacturer Part Number
KSZ8873MLL
Description
IC ETHERNET SWITCH 3PORT 64-LQFP
Manufacturer
Micrel Inc
Specifications of KSZ8873MLL
Data Rate
100Mbps
Controller Type
Ethernet Switch Controller
Interface
MII
Voltage - Supply
1.8V, 2.5V, 3.3V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
No. Of Ports
3
Ethernet Type
IEEE 802.3u
Supply Current
115mA
Supply Voltage Range
2.5V, 3.3V
Digital Ic Case Style
LQFP
No. Of Pins
64
Svhc
No SVHC (15-Dec-2010)
Base
RoHS Compliant
Number Of Primary Switch Ports
3
Internal Memory Buffer Size
32
Fiber Support
No
Integrated Led Drivers
Yes
Phy/transceiver Interface
MII
Power Supply Type
Analog/Digital
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
1.89/3.465V
Operating Temperature Classification
Commercial
Interface Type
MII, RMII
Operating Temperature Range
0°C To +70°C
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
576-3459
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
KSZ8873MLL
Manufacturer:
Micrel Inc
Quantity:
1 934
Company:
Part Number:
KSZ8873MLL
Manufacturer:
ADI
Quantity:
27
Company:
Part Number:
KSZ8873MLL AM
Manufacturer:
Micrel
Quantity:
1 638
Company:
Part Number:
KSZ8873MLLJ
Manufacturer:
Micrel
Quantity:
323
Micrel, Inc.
IGMP Support
For Internet Group Management Protocol (IGMP) support in layer 2, the KSZ8873MLL/FLL/RLL provides two
components:
IGMP Snooping
The KSZ8873MLL/FLL/RLL traps IGMP packets and forwards them only to the processor (port 3). The IGMP packets are
identified as IP packets (either Ethernet IP packets, or IEEE 802.3 SNAP IP packets) with IP version = 0x4 and protocol
version number = 0x2.
Multicast Address Insertion in the Static MAC Table
Once the multicast address is programmed in the Static MAC Table, the multicast session is trimmed to the subscribed
ports, instead of broadcasting to all ports.
To enable IGMP support, set register 5 bit [6] to ‘1’. Also, Tail Tagging Mode needs to be enabled, so that the processor
knows which port the IGMP packet was received on. This is achieved by setting both register 3 bit [6] and register 48 bit
[2] to ‘1’.
Port Mirroring Support
KSZ8873MLL/FLL/RLL supports “Port Mirroring” comprehensively as:
September 2010
“receive only” mirror on a port
All the packets received on the port are mirrored on the sniffer port. For example, port 1 is programmed to be
“receive sniff” and port 3 is programmed to be the “sniffer port”. A packet received on port 1 is destined to port 2
after the internal lookup. The KSZ8873MLL/FLL/RLL forwards the packet to both port 2 and port 3. The
KSZ8873MLL/FLL/RLL can optionally even forward “bad” received packets to the “sniffer port”.
“transmit only” mirror on a port
All the packets transmitted on the port are mirrored on the sniffer port. For example, port 1 is programmed to be
“transmit sniff” and port 3 is programmed to be the “sniffer port”. A packet received on port 2 is destined to port 1
after the internal lookup. The KSZ8873MLL/FLL/RLL forwards the packet to both port 1 and port 3.
“receive and transmit” mirror on two ports
All the packets received on port A and transmitted on port B are mirrored on the sniffer port. To turn on the “AND”
feature, set register 5 bit [0] to ‘1’. For example, port 1 is programmed to be “receive sniff”, port 2 is programmed
to be “transmit sniff”, and port 3 is programmed to be the “sniffer port”. A packet received on port 1 is destined to
port 2 after the internal lookup. The KSZ8873MLL/FLL/RLL forwards the packet to both port 2 and port 3.
Ingress to Port 3 (Host -> KSZ8873MLL/FLL/RLL)
Bit [1,0]
0,0
0,1
1,0
1,1
Bit [3,2]
0,0
0,1
1,0
1,1
Egress from Port 3 (KSZ8873MLL/FLL/RLL->Host)
Bit [0]
0
1
Figure 8. Tail Tag Rules
Destination Port
Normal (Address Look up)
Port 1
Port 2
Port 1 and 2
Frame Priority
Priority 0
Priority 1
Priority 2
Priority 3
Source Port
Port 1
Port 2
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KSZ8873MLL/FLL/RLL
M9999-092309-1.2