LAN9311-NU SMSC, LAN9311-NU Datasheet - Page 57

IC ETHER SW 2PRT 16BIT 128-VTQFP

LAN9311-NU

Manufacturer Part Number
LAN9311-NU
Description
IC ETHER SW 2PRT 16BIT 128-VTQFP
Manufacturer
SMSC
Type
Two Port Managed Ethernet Switchr
Datasheets

Specifications of LAN9311-NU

Controller Type
Ethernet Switch Controller
Interface
Serial EEPROM
Voltage - Supply
3.3V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-TQFP, 128-VQFP
Product
Ethernet Switches
Number Of Transceivers
1
Standard Supported
802.3, 802.3u
Data Rate
10 MB, 100 MB
Supply Voltage (max)
3.3 V
Supply Voltage (min)
0 V
Maximum Operating Temperature
+ 70 C
Ethernet Connection Type
10 Base-T, 100 Base-TX
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
For Use With
638-1076 - EVALUATION BOARD LAN9311-NU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
638-1075

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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
6.2.2
CSR_BUSY = 0
Switch Fabric CSR Reads
To perform a read of an individual switch fabric register, the read cycle must be initiated by performing
a single write to the
CSR_BUSY (bit 31) set, the CSR_ADDRESS field (bits 15:0) set to the desired register address, the
R_nW (bit 30) set, and the AUTO_INC and AUTO_DEC fields cleared. Valid data is available for
reading when the CSR_BUSY bit is cleared, indicating that the data can be read from the
CSR Interface Data Register
A second read method may be used which utilizes the auto increment/decrement function of the
Fabric CSR Interface Command Register (SWITCH_CSR_CMD)
addresses. When using this method, the
(SWITCH_CSR_CMD)
decrement(AUTO_DEC) bit set, the CSR_ADDRESS field written with the desired register address,
and the R_nW bit set. The completion of a read cycle is indicated by the clearing of the CSR_BUSY
bit, at which time the data can be read from the
(SWITCH_CSR_DATA). When the data is read, the address in the
Command Register (SWITCH_CSR_CMD)
read cycle is started automatically. The user should clear the AUTO_INC and AUTO_DEC bits before
reading the last data to avoid an unintended read cycle.
Figure 6.2
periods as specified in
noted.
CSR Write
Write Data
Command
Command
Register
Register
Register
illustrates the process required to perform a switch fabric CSR read. The minimum wait
Read
Write
Idle
Figure 6.1 Switch Fabric CSR Write Access Flow Diagram
min wait period
CSR_BUSY = 1
Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD)
Table 8.1, “Read After Write Timing Rules,” on page 103
must first be written with the auto increment(AUTO_INC) or auto
CSR_BUSY = 0
(SWITCH_CSR_DATA).
CSR Write Auto
DATASHEET
Increment /
Decrement
Command
Write Data
Command
Register
Register
Register
Write
Read
Idle
57
is incremented or decremented accordingly, and another
min wait period
Switch Fabric CSR Interface Command Register
CSR_BUSY = 1
Switch Fabric CSR Interface Data Register
CSR_BUSY = 0
CSR Write Direct
Address
for reading sequential register
Command
Register
Register
Range
Switch Fabric CSR Interface
Direct
Write
Read
Data
Idle
min wait period
CSR_BUSY = 1
Revision 1.7 (06-29-10)
are required where
Switch Fabric
Switch
with

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