ISP1160BD01TM ST-Ericsson Inc, ISP1160BD01TM Datasheet - Page 31

IC USB HOST CTRL FULL-SPD 64LQFP

ISP1160BD01TM

Manufacturer Part Number
ISP1160BD01TM
Description
IC USB HOST CTRL FULL-SPD 64LQFP
Manufacturer
ST-Ericsson Inc
Datasheet

Specifications of ISP1160BD01TM

Controller Type
USB 2.0 Controller
Interface
Parallel
Voltage - Supply
3.3V, 5V
Current - Supply
47mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-1878-2
ISP1160BD/01,118
ISP1160BD01-T

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ISP1160BD01TM
Manufacturer:
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Quantity:
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Part Number:
ISP1160BD01TM
Manufacturer:
ST
Quantity:
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Product data
Fig 21. HC time domain behavior: example 1.
Fig 22. HC time domain behavior: example 2.
SOF
interrupt
ISO
(frame N)
9.5.1 Time domain behavior
(frame N)
read ISO_A(N 1) write ISO_A(N 1)
ITL0BufferDone and ITL0BufferFull bits will be cleared automatically. This also
applies to the ITL1 buffer because ITL0 and ITL1 are Ping-Pong structured buffers. To
recover from this state, a power-on reset or software reset will have to be applied.
In example 1
scenario before the next interrupt. Note that on the ISO interrupt of frame N:
In example 2
when the ISO interrupt of the next frame (N
AT traffic in frame N
AT part is simply postponed until frame N
mechanism is back to the normal operation. This simple mechanism ensures, among
other things, that Control transfers are not dropped systematically from the USB in
case of an overloaded microprocessor.
In example 3
(SOF) of the next frame has occurred. This will result in undefined behavior for the
ISO data on the USB bus in frame N
is corrupted or not). The HC should not raise an AT interrupt in frame N
on USB
The ISO packet for frame N
The AT packet for frame N
traffic
(frame N 1)
(Figure
interrupt
(Figure
(Figure
AT
(frame N 1)
Rev. 05 — 24 December 2004
21), the CPU is fast enough to read back and download a
22), the microprocessor is still busy transferring the AT data
23), the ISO part is still being written while the Start of Frame
1. The HC does not raise an AT interrupt in frame N
read AT(N)
1 will be written.
1 will be written
(frame N 2)
(frame N 2)
1 (depending on whether the exact timing data
write AT(N 1)
2. On the AT N
1) is raised. As a result, there will be no
Embedded USB Host Controller
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
(frame N 3)
(frame N 3)
2 interrupt, the transfer
MGT955
ISP1160
MGT954
1.
1. The
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