ISP1160BD01TM ST-Ericsson Inc, ISP1160BD01TM Datasheet - Page 46

• Manufacturer Part Number: ISP1160BD01TM
• Description: IC USB HOST CTRL FULL-SPD 64LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1160BD01TM

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1878-2; ISP1160BD/01,118; ISP1160BD01-T

Philips Semiconductors
Table 22:
9397 750 13963
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcFmRemaining register: bit allocation
R/W
R/W
R/W
FRT
23
15
31
23
R
R
0
0
7
1
0
0
10.2.2 HcFmRemaining register (R: 0EH)
reserved
Table 21:
The HcFmRemaining register is a 14-bit down counter showing the bit time remaining
in the current frame.
Code (Hex): 0E — read
Bit
31
30 to 16
15 to 14
13 to 0
R/W
R/W
R/W
22
14
30
22
R
R
0
0
6
1
0
0
HcFmInterval register: bit description
Symbol
FIT
FSMPS
[14:0]
-
FI[13:0]
R/W
R/W
R/W
21
13
29
21
R
R
0
1
5
0
0
0
Rev. 05 — 24 December 2004
Description
FrameIntervalToggle: The HCD toggles this bit whenever it loads
a new value to FrameInterval.
FSLargestDataPacket: Specifies a value which is loaded into the
Largest Data Packet Counter at the beginning of each frame. The
counter value represents the largest amount of data in bits which
can be sent or received by the HC in a single transaction at any
given time without causing a scheduling overrun. The field value is
calculated by the HCD.
reserved
FrameInterval: Specifies the interval between two consecutive
SOFs in bit times. The default value is 11999. The HCD must save
the current value of this field before resetting the HC. Setting the
HostControllerReset field of the HcCommandStatus register will
cause the HC to reset this field to its default value. HCD may
choose to restore the saved value upon completing the reset
sequence.
R/W
R/W
R/W
20
12
28
20
R
R
0
0
4
1
0
0
FSMPS[7:0]
reserved
FI[7:0]
reserved
R/W
R/W
R/W
19
11
27
19
R
R
0
1
3
1
0
0
FI[13:8]
Embedded USB Host Controller
R/W
R/W
R/W
18
10
26
18
R
R
0
1
2
1
0
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
R/W
R/W
R/W
17
25
17
R
R
0
9
1
1
1
0
0
ISP1160
R/W
R/W
R/W
16
24
16
R
R
0
8
0
0
1
0
0
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