ISP1160BD01TM ST-Ericsson Inc, ISP1160BD01TM Datasheet - Page 59

IC USB HOST CTRL FULL-SPD 64LQFP

ISP1160BD01TM

Manufacturer Part Number
ISP1160BD01TM
Description
IC USB HOST CTRL FULL-SPD 64LQFP
Manufacturer
ST-Ericsson Inc
Datasheet

Specifications of ISP1160BD01TM

Controller Type
USB 2.0 Controller
Interface
Parallel
Voltage - Supply
3.3V, 5V
Current - Supply
47mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-1878-2
ISP1160BD/01,118
ISP1160BD01-T

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISP1160BD01TM
Manufacturer:
ST-Ericsson Inc
Quantity:
10 000
Part Number:
ISP1160BD01TM
Manufacturer:
ST
Quantity:
20 000
Philips Semiconductors
Table 38:
9397 750 13963
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcDMAConfiguration register: bit allocation
reserved
R/W
R/W
15
0
7
0
10.4.2 HcDMAConfiguration register (R/W: 21H/A1H)
Table 37:
Code (Hex): 21 — read
Code (Hex): A1 — write
Table 39:
Bit
2
1
0
Bit
15 to 7
6 to 5
4
3
R/W
R/W
14
0
6
0
BurstLen[1:0]
Symbol
InterruptOutputPolarity
InterruptPinTrigger
InterruptPinEnable
Symbol
-
BurstLen[1:0] 00 — single-cycle burst DMA
DMAEnable
-
HcHardwareConfiguration register: bit description
HcDMAConfiguration register: bit description
R/W
R/W
13
0
5
0
Rev. 05 — 24 December 2004
Description
reserved
01 — 4-cycle burst DMA
10 — 8-cycle burst DMA
11 — reserved
0 — DMA is terminated
1 — DMA is enabled
This bit will be reset to logic 0 when DMA transfer is completed.
reserved
Enable
DMA
R/W
R/W
12
0
4
0
reserved
Description
0 — active LOW
1 — active HIGH
0 — interrupt is level-triggered
1 — interrupt is edge-triggered
This bit is used as pin INT’s master interrupt enable and
should be used together with register
Hc PInterruptEnable to enable pin INT.
0 — pin INT is disabled
1 — pin INT is enabled
reserved
R/W
R/W
11
0
3
0
Counter
Embedded USB Host Controller
Select
DMA
R/W
R/W
10
0
2
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
…continued
DataSelect
ITL_ATL_
R/W
R/W
9
0
1
0
ISP1160
WriteSelect
DMARead
R/W
R/W
8
0
0
0
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