DP83256VF National Semiconductor, DP83256VF Datasheet - Page 108

• Manufacturer Part Number: DP83256VF
• Description: IC FDDI LAYER CTRLR 160PQFP
• Manufacturer: National Semiconductor
• Series: PLAYER+™r

Specifications of DP83256VF

• Controller Type: physical layer controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Interface: -
• Other names: *DP83256VF

Symbol
SP0
SP1
SP2
EP0
EP1
EP2
CS
CR
E RST
6 0 Signal Descriptions
MISCELLANEOUS INTERFACE
The Miscellaneous Interface consist of a reset signal user definable sense signals and user definable enable signals
Pin
116
63
65
67
64
66
68
69
70
I O
O
O
O
O
I
I
I
I
I
Reset An active low TTL input signal which clears all registers The signal must be kept asserted for a
minimum amount of time Once the E RST signal is asserted the PLAYER
the specified amount of time to reset internal logic Note that bit zero of the Mode Register will be set to
zero (i e Stop Mode) See section 4 2 Stop Mode of Operation for more information
User Definable Sense Pin 0 A TTL input signal from a user defined source Sense Bit 0 (SB0) of the
User Definable Register (UDR) will be set to one if the signal is asserted for a minimum of 160 ns Once
the asserted signal is latched Sense Bit 0 can only be cleared through the Control Bus Interface even if
the signal is deasserted This ensures that the Control Bus Interface will record the source of events
which can cause interrupts
User Definable Sense Pin 1 A TTL input signal from a user defined source Sense Bit 1 (SB1) of the
User Definable Register (UDR) will be set to one if the signal is asserted for a minimum of 160 ns Once
the asserted signal is latched Sense Bit 1 can only be cleared through the Control Bus Interface even if
the signal is deasserted This ensures that the Control Bus Interface will record the source of events
which can cause interrupts
User Definable Sense Pin 2 A TTL input signal from a user defined source Sense Bit 2 (SB2) of the
User Definable Register (UDR) will be set to one if the signal is asserted for a minimum of 160 ns Once
the asserted signal is latched Sense Bit 2 can only be cleared through the Control Bus Interface even if
the signal is deasserted This ensures that the Control Bus Interface will record the source of events
which can cause interrupts
User Definable Enable Pin 0 A TTL output signal allowing control of external logic through the Control
Bus Interface EP0 is asserted deasserted through Enable Bit 0 (EB0) of the User Definable Register
(UDR) When Enable Bit 0 is set to zero EP0 is deasserted When Enable Bit 0 is set to one EP0 is
asserted
User Definable Enable Pin 1 A TTL output signal allowing control of external logic through the Control
Bus Interface EP1 is asserted deasserted through Enable Bit 1 (EB1) of the User Definable Register
(UDR) When Enable Bit 1 is set to zero EP1 is deasserted When Enable Bit 1 is set to one EP1 is
asserted
User Definable Enable Pin 2 A TTL output signal allowing control of external logic through the Control
Bus Interface EP2 is asserted deasserted through Enable Bit 2 (EB2) of the User Definable Register
(UDR) When Enable Bit 2 is set to zero EP2 is deasserted When Enable Bit 2 is set to one EP2 is
asserted
Cascade Start A TTL input signal used to synchronize cascaded PLAYER
applications
The signal is asserted when all of the cascaded PLAYER
the Mode Register (MR) set to one and all of the Cascade Ready (CR) pins of the cascaded PLAYER
devices have been released
When Cascade Mode is not being used this input should be tied to Ground
For further information refer to section 4 4 Cascade Mode of Operation
Cascade Ready An Open Drain output signal used to synchronize cascaded PLAYER
point-to-point applications
The signal is released (i e an Open Drain line is released) when all the cascaded PLAYER
have the Cascade Mode (CM) bit of the Mode Register (MR) is set to one and a JK symbol pair has been
received
When Cascade Mode is not being used this input should be left Not Connected (N C)
For further information refer to section 4 4 Cascade Mode of Operation
(Continued)
108
Description
a
devices have the Cascade Mode (CM) bit of
a
a
device should be allowed
devices in point-to-point
a
devices in
a
devices
a