DP83256VF National Semiconductor, DP83256VF Datasheet - Page 85

• Manufacturer Part Number: DP83256VF
• Description: IC FDDI LAYER CTRLR 160PQFP
• Manufacturer: National Semiconductor
• Series: PLAYER+™r

Specifications of DP83256VF

• Controller Type: physical layer controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Interface: -
• Other names: *DP83256VF

D0-D2
D3
D4
D5
D6-D7
5 0 Registers
5 41 CLOCK GENERATION MODULE REGISTER (CGMREG)
This register is used to enable or disable the 125 MHz ECL Transmit clock outputs These outputs are not required for use in a
standard FDDI board implementation and are disabled by default to reduce high frequency noise
These TXC outputs are included for support of alternate FDDI PMDs such as unshielded twisted pair copper cable
DO NOT WRITE TO RESERVED REGISTER BITS Writes to reserved register bits could prevent proper device operation
Therefore read the register first and then write it back with the non-reserved bits set to the desired value
ACCESS RULES
Bit
RES
D7
ADDRESS
RES
TXCE
RES
FLTREN
RES
Symbol
3Bh
RES
D6
RESERVED BITS DO NOT CHANGE THE VALUE OF THESE BITS Changes to reserved register bits could
prevent proper device operation
TRANSMIT CLOCK ENABLE When bit is set to 1 125 MHz ECL TXC outputs are enabled When this bit is
reset to 0 TXC outputs are disabled TXC outputs are disabled on reset
Note TXC clocks are only available on the 160-pin DP83257 PLAYER
RESERVED BITS DO NOT CHANGE THE VALUE OF THESE BITS Changes to reserved register bits could
prevent proper device operation
FILTER ENABLE When bit is set to 1 the internal loop filter node is connected to the LPFLTR pin for
diagnostic viewing This bit is reset to 0 by default which disconnects the filter node from the LPFLTR pin
Note In normal operation this bit should be disabled (
RESERVED BITS DO NOT CHANGE THE VALUE OF THESE BITS Changes to reserved register bits could
prevent proper device operation
(Continued)
Always
READ
FLTREN
D5
RES
D4
WRITE
Always
TXCE
D3
e
85
0)
Description
RES
D2
a
device
RES
D1
RES
D0