DP83256VF National Semiconductor, DP83256VF Datasheet - Page 23

• Manufacturer Part Number: DP83256VF
• Description: IC FDDI LAYER CTRLR 160PQFP
• Manufacturer: National Semiconductor
• Series: PLAYER+™r

Specifications of DP83256VF

• Controller Type: physical layer controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Interface: -
• Other names: *DP83256VF

3 0 Functional Description
3 5 CLOCK GENERATION MODULE
The Clock Generation Module is an integrated phase locked
loop that generates all of the required clock signals for the
PLAYER
single 12 5 MHz reference
The Clock Generation Module features
The Clock Generation Module is comprised of 6 main func-
tional blocks
See Figure 3-18 Clock Generation Module Block Diagram
REFERENCE SELECTOR
The Reference Selector block allows the user to choose
between 2 sources for the Clock Generation Module’s
12 5 MHz reference clock
The simplest reference clock source option is to use an
external 12 5 MHz reference signal fed into the REF IN
input This input can come from a crystal oscillator module
or from a Local Byte Clock generated by another PLAYER
device Using the appropriate crystal oscillator ensures cor-
rect operating frequency without having to adjust any dis-
crete components
Using an LBC clock from another PLAYER
one PLAYER
other PLAYER
Reference Selector
Phase Comparator
Loop Filter
250 MHz Voltage Controlled Oscillator
Output Phasing and Divide by 10
High precision clock timing generated from a single
12 5 MHz reference
Multiple precision phased (8 ns 16 ns) 12 5 MHz Local
Byte Clocks to eliminate timing skew in large multi-board
concentrator configurations
LBC timing which is insensitive to loading variations over
a wide range (20 pF to 70 pF) of LBC loads
A selectable dual frequency system clock
Low clock edge jitter due to high VCO stability
a
device and the rest of an FDDI system from a
a
a
device to create a master clock to which
devices in a system can be synchronized
FIGURE 3-18 Clock Generation Module Block Diagram
a
(Continued)
device allows
a
23
Another reference clock source option is a local 12 5 MHz
crystal circuit An example crystal circuit with component
values is shown in Figure 3-19 This circuit is designed to
operate with a crystal that has a C
values may need to be slightly adjusted for an individual
application to accomodate differences in parasitic loading
The REF SEL signal selects between the two references
Component Values
Crystal 12 50000 MHz
R
C
C
C
PHASE COMPARATOR
The Phase Comparator uses two signal inputs the selected
12 5 MHz reference from the Reference Select Block and a
Local Byte Clock that has been selected for the feedback
input FBK IN Typically LBC1 is used as the feedback
clock
The Phase Comparator generates a pulse of current that is
proportional to the phase difference between the two sig-
nals The current pulses are used to charge and discharge a
control voltage on the internal Loop Filter This control volt-
age is used to minimize the phase difference between the
two signals
LOOP FILTER
The Loop Filter is a simple internal filter made up of one
capacitor in parallel with a serial capacitor and resistor com-
bination One end of the filter is connected to Ground and
the other node is driven by the Phase Comparator and con-
trols the internal 250 MHz Voltage Controlled Oscillator
This node can be examined for diagnostic purposes on the
LPFLTR pin when the FLTREN bit of the CGMREG register
is enabled The LPFLTR pin is provided for diagnostic pur-
poses only and should not be connected in any application
ISO
IN
OUT
270
56 pF (1%)
54 pF (1%)
54 pF (1%)
5%
FIGURE 3-19 Crystal Circuit
L
of 15 pF The capacitor
TL F 11708 – 21
TL F 11708 – 22