PIC18F452-I/L Microchip Technology Inc., PIC18F452-I/L Datasheet - Page 110
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PIC18F452-I/L
Manufacturer Part Number
PIC18F452-I/L
Description
44 PIN, 32 KB FLASH, 1536 RAM, 34 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F452-IL.pdf
(332 pages)
Specifications of PIC18F452-I/L
A/d Inputs
8-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
36
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin PLCC
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC18FXX2
11.1
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
The Operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
FIGURE 11-1:
FIGURE 11-2:
DS39564C-page 108
T13CKI/T1OSO
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
T1CKI/T1OSO
T1OSI
TMR1IF
Overflow
Interrupt
Flag bit
Data Bus<7:0>
Timer1 Operation
Write TMR1L
Read TMR1L
TMR1IF
Overflow
Interrupt
Flag Bit
T1OSI
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
TIMER1 BLOCK DIAGRAM
8
T1OSC
High Byte
TMR1H
Timer 1
8
TMR1H
T1OSC
8
TMR1
TMR1
Oscillator
Enable
T1OSCEN
T1OSCEN
Enable
Oscillator
TMR1L
TMR1L
8
(1)
CLR
(1)
CLR
Clock
Internal
F
OSC
Clock
F
Internal
OSC
/4
TMR1ON
CCP Special Event Trigger
On/Off
/4
TMR1CS
TMR1ON
CCP Special Event Trigger
on/off
1
0
When TMR1CS = 0, Timer1 increments every instruc-
tion cycle. When TMR1CS = 1, Timer1 increments on
every rising edge of the external clock input or the
Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored, and the pins are read as ‘0’.
Timer1 also has an internal “RESET input”. This
RESET can be generated by the CCP module
(Section 14.0).
TMR1CS
1
0
T1CKPS1:T1CKPS0
T1SYNC
Prescaler
1, 2, 4, 8
T1CKPS1:T1CKPS0
T1SYNC
Prescaler
0
1
1, 2, 4, 8
2
1
0
2
© 2006 Microchip Technology Inc.
Synchronized
Clock Input
Synchronize
SLEEP Input
Synchronized
Clock Input
Synchronize
SLEEP Input
det
det
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