PIC18F452-I/L Microchip Technology Inc., PIC18F452-I/L Datasheet - Page 190

• Manufacturer Part Number: PIC18F452-I/L
• Description: 44 PIN, 32 KB FLASH, 1536 RAM, 34 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F452-I/L

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18FXX2
17.5
An A/D conversion can be started by the “special event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as 1011 and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/
DONE bit will be set, starting the A/D conversion, and
the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
TABLE 17-2:
DS39564C-page 188
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
ADRESH
ADRESL
ADCON0
ADCON1
PORTA
TRISA
PORTE
LATE
TRISE
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear.
Name
Use of the CCP2 Trigger
PSPIF
PSPIE
PSPIP
A/D Result Register
A/D Result Register
ADCS1
GIEH
ADFM
Bit 7
GIE/
IBF
—
—
—
—
—
—
—
(1)
(1)
(1)
SUMMARY OF A/D REGISTERS
PORTA Data Direction Register
ADCS0
ADCS2
PEIE/
GIEL
ADIF
ADIE
ADIP
Bit 6
OBF
RA6
—
—
—
—
—
TMR0IE
CHS2
RCIF
RCIE
RCIP
IBOV
Bit 5
RA5
—
—
—
—
—
—
PSPMODE
INT0IE
CHS1
EEIE
EEIP
Bit 4
TXIF
TXIE
TXIP
EEIF
RA4
—
—
—
PCFG3
SSPIF
SSPIE
SSPIP
BCLIF
BCLIE
BCLIP
CHS0
RBIE
Bit 3
RA3
—
—
—
PORTE Data Direction bits
GO/DONE
(moving ADRESH/ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition done before the “special
event trigger” sets the GO/DONE bit (starts a
conversion).
If the A/D module is not enabled (ADON is cleared), the
“special event trigger” will be ignored by the A/D
module, but will still reset the Timer1 (or Timer3)
counter.
TMR0IF
CCP1IE
CCP1IP
CCP1IF
PCFG2
LATE2
LVDIE
LVDIP
LVDIF
Bit 2
RA2
RE2
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
PCFG1
INT0IF
LATE1
Bit 1
RA1
RE1
—
TMR1IF
TMR1IE 0000 0000 0000 0000
TMR1IP 0000 0000 0000 0000
CCP2IE
CCP2IP
CCP2IF
PCFG0
LATE0
ADON
RBIF
Bit 0
RA0
RE0
© 2006 Microchip Technology Inc.
0000 000x 0000 000u
0000 0000 0000 0000
---0 0000 ---0 0000
---0 0000 ---0 0000
---1 1111 ---1 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 00-0 0000 00-0
---- -000 ---- -000
--0x 0000 --0u 0000
--11 1111 --11 1111
---- -000 ---- -000
---- -xxx ---- -uuu
0000 -111 0000 -111
POR, BOR
Value on
All Other
Value on
RESETS