PIC18F452-I/L Microchip Technology Inc., PIC18F452-I/L Datasheet - Page 43

• Manufacturer Part Number: PIC18F452-I/L
• Description: 44 PIN, 32 KB FLASH, 1536 RAM, 34 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F452-I/L

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

4.7.1
The PIC18FXX2 devices have four two-word instruc-
tions: MOVFF, CALL, GOTO and LFSR. The second
word of these instructions has the 4 MSBs set to 1’s
and is a special kind of NOP instruction. The lower 12
bits of the second word contain data to be used by the
instruction. If the first word of the instruction is exe-
cuted, the data in the second word is accessed. If the
4.8
Lookup tables are implemented two ways. These are:
• Computed GOTO
• Table Reads
4.8.1
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL).
A lookup table can be formed with an ADDWF PCL
instruction and a group of RETLW 0xnn instructions.
WREG is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW 0xnn
instructions, that returns the value 0xnn to the calling
function.
The offset value (value in WREG) specifies the number
of bytes that the program counter should advance.
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
© 2006 Microchip Technology Inc.
EXAMPLE 4-3:
CASE 1:
Object Code
CASE 2:
Object Code
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
Note:
Lookup Tables
The ADDWF
update PCLATH and PCLATU. A read
operation on PCL must be performed to
update PCLATH and PCLATU.
TWO-WORD INSTRUCTIONS
COMPUTED GOTO
TWO-WORD INSTRUCTIONS
PCL instruction does not
Source Code
TSTFSZ
MOVFF
Source Code
TSTFSZ
ADDWF
ADDWF
MOVFF
REG1
REG1, REG2 ; No, execute 2-word instruction
REG3
REG1
REG1, REG2 ; Yes
REG3
; is RAM location 0?
; 2nd operand holds address of REG2
; continue code
; is RAM location 0?
; 2nd operand becomes NOP
; continue code
second word of the instruction is executed by itself (first
word was skipped), it will execute as a NOP. This action
is necessary when the two-word instruction is preceded
by a conditional instruction that changes the PC. A pro-
gram example that demonstrates this concept is shown
in Example 4-3. Refer to Section 20.0 for further details
of the instruction set.
4.8.2
A better method of storing data in program memory
allows 2 bytes of data to be stored in each instruction
location.
Lookup table data may be stored 2 bytes per program
word by using table reads and writes. The table pointer
(TBLPTR) specifies the byte address and the table
latch (TABLAT) contains the data that is read from, or
written to program memory. Data is transferred to/from
program memory, one byte at a time.
A description of the Table Read/Table Write operation
is shown in Section 3.0.
TABLE READS/TABLE WRITES
PIC18FXX2
DS39564C-page 41