PIC18F452-I/L Microchip Technology Inc., PIC18F452-I/L Datasheet - Page 287

• Manufacturer Part Number: PIC18F452-I/L
• Description: 44 PIN, 32 KB FLASH, 1536 RAM, 34 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F452-I/L

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TABLE 22-18: MASTER SSP I
© 2006 Microchip Technology Inc.
100
101
102
103
90
91
106
107
92
109
110
D102
Note 1: Maximum pin capacitance = 10 pF for all I
Param.
No.
2: A Fast mode I
T
T
T
T
T
T
T
T
T
T
T
C
Symbol
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL
signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode) before the SCL line
is released.
SU
SU
SU
AA
HIGH
LOW
R
F
HD
HD
BUF
B
:
:
:
:
:
STA
DAT
STO
STA
DAT
Clock high time
Clock low time
SDA and SCL
rise time
SDA and SCL
fall time
START condition
setup time
START condition
hold time
Data input
hold time
Data input
setup time
STOP condition
setup time
Output valid from
clock
Bus free time
Bus capacitive loading
2
C bus device can be used in a Standard mode I
Characteristic
2
C BUS DATA REQUIREMENTS
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
(1)
(1)
(1)
(1)
(1)
(1)
(1)
2
C pins.
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
OSC
OSC
OSC
OSC
OSC
OSC
20 + 0.1 C
20 + 0.1 C
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
Min
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
250
100
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
1.3
4.7
—
—
—
—
—
—
—
0
0
B
B
2
C bus system, but parameter #107
1000
1000
3500
1000
Max
300
300
300
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PIC18FXX2
C
10 to 400 pF
V
V
Only relevant for
Repeated START
condition
After this period, the first
clock pulse is generated
(Note 2)
Time the bus must be free
before a new transmission
can start
B
DD
DD
is specified to be from
DS39564C-page 285
4.2V
4.2V
Conditions
250 ns