PIC18F2550-I/SP Microchip Technology Inc., PIC18F2550-I/SP Datasheet - Page 141

• Manufacturer Part Number: PIC18F2550-I/SP
• Description: Microcontroller; 32 KB Flash; 2048 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2550-I/SP

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 23
• Interface: I2C/SPI/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

14.2
Timer3 can be configured for 16-bit reads and writes
(see Figure 14-2). When the RD16 control bit
(T3CON<7>) is set, the address for TMR3H is mapped
to a buffer register for the high byte of Timer3. A read
from TMR3L will load the contents of the high byte of
Timer3 into the Timer3 high byte buffer. This provides
the user with the ability to accurately read all 16 bits of
Timer1 without having to determine whether a read of
the high byte, followed by a read of the low byte, has
become invalid due to a rollover between reads.
A write to the high byte of Timer3 must also take place
through the TMR3H Buffer register. The Timer3 high
byte is updated with the contents of TMR3H when a
write occurs to TMR3L. This allows a user to write all
16 bits to both the high and low bytes of Timer3 at once.
The high byte of Timer3 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer3 High Byte Buffer register.
Writes to TMR3H do not clear the Timer3 prescaler.
The prescaler is only cleared on writes to TMR3L.
14.3
The Timer1 internal oscillator may be used as the clock
source for Timer3. The Timer1 oscillator is enabled by
setting the T1OSCEN (T1CON<3>) bit. To use it as the
Timer3 clock source, the TMR3CS bit must also be set.
As previously noted, this also configures Timer3 to
increment on every rising edge of the oscillator source.
The Timer1 oscillator is described in Section 12.0
“Timer1 Module”.
TABLE 14-1:
© 2006 Microchip Technology Inc.
INTCON GIE/GIEH PEIE/GIEL
PIR2
PIE2
IPR2
TMR3L
TMR3H
T1CON
T3CON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
Name
Timer3 16-Bit Read/Write Mode
Using the Timer1 Oscillator as the
Timer3 Clock Source
Timer3 Register Low Byte
Timer3 Register High Byte
OSCFIF
OSCFIE
OSCFIP
RD16
RD16
Bit 7
REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
T3CCP2
T1RUN
CMIF
CMIE
CMIP
Bit 6
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS
T3CKPS1 T3CKPS0
TMR0IE
USBIF
USBIE
USBIP
Bit 5
PIC18F2455/2550/4455/4550
INT0IE
EEIE
EEIP
Bit 4
EEIF
Preliminary
T3CCP1
BCLIF
BCLIE
BCLIP
RBIE
Bit 3
14.4
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and overflows to 0000h. The
Timer3 interrupt, if enabled, is generated on overflow
and is latched in interrupt flag bit, TMR3IF (PIR2<1>).
This interrupt can be enabled or disabled by setting or
clearing the Timer3 Interrupt Enable bit, TMR3IE
(PIE2<1>).
14.5
If the CCP2 module is configured to generate a
(CCP2M3:CCP2M0 = 1011), this signal will reset
Timer3. It will also start an A/D conversion if the A/D
module is enabled (see Section 15.3.4 “Special
Event Trigger” for more information.).
The module must be configured as either a timer or
synchronous counter to take advantage of this feature.
When used this way, the CCPR2H:CCPR2L register
pair effectively becomes a period register for Timer3.
If Timer3 is running in Asynchronous Counter mode,
the Reset operation may not work.
In the event that a write to Timer3 coincides with a
Special Event Trigger from a CCP module, the write will
take precedence.
Special
Note:
T3SYNC TMR3CS
Timer3 Interrupt
Resetting Timer3 Using the CCP
Special Event Trigger
TMR0IF
HLVDIF
HLVDIE
HLVDIP
Bit 2
Event
The Special Event Triggers from the
CCP2 module will not set the TMR3IF
interrupt flag bit (PIR2<1>).
Trigger
TMR3IF
TMR3IE
TMR3IP
INT0IF
Bit 1
in
TMR1ON
TMR3ON
CCP2IE
CCP2IP
CCP2IF
RBIF
Bit 0
DS39632C-page 139
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Values
Reset
51
54
54
54
53
53
52
53
mode