PIC18F2550-I/SP Microchip Technology Inc., PIC18F2550-I/SP Datasheet - Page 344
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC18F2550-I/SP
Manufacturer Part Number
PIC18F2550-I/SP
Description
Microcontroller; 32 KB Flash; 2048 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F2550-ISP.pdf
(430 pages)
Specifications of PIC18F2550-I/SP
A/d Inputs
10-Channel, 10-Bit
Comparators
2
Cpu Speed
12 MIPS
Eeprom Memory
256 Bytes
Input Output
23
Interface
I2C/SPI/USART/USB
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
32K Bytes
Ram Size
2K Bytes
Speed
48 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F2550-I/SP
Manufacturer:
MICROCHIP
Quantity:
2 100
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PIC18F2455/2550/4455/4550
SLEEP
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
† If WDT causes wake-up, this bit is cleared.
DS39632C-page 342
Q Cycle Activity:
Before Instruction
After Instruction
Decode
TO =
PD =
TO =
PD =
Q1
?
?
1 †
0
operation
Enter Sleep mode
None
00h
0
1
0
TO, PD
The Power-Down status bit (PD) is
cleared. The Time-out status bit (TO)
is set. Watchdog Timer and its
postscaler are cleared.
The processor is put into Sleep mode
with the oscillator stopped.
1
1
SLEEP
SLEEP
No
Q2
0000
WDT postscaler,
TO,
PD
WDT,
0000
Process
Data
Q3
0000
Go to
Sleep
Q4
0011
Preliminary
SUBFWB
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example 1:
Example 2:
Example 3:
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
REG
W
C
REG
W
C
Z
N
REG
W
C
REG
W
C
Z
N
REG
W
C
REG
W
C
Z
N
Q1
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
register ‘f’
(W) – (f) – (C)
Subtract register ‘f’ and Carry flag
1
Subtract f from W with Borrow
0
d
a
N, OV, C, DC, Z
(borrow) from W (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored in
register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used
to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” for details.
1
SUBFWB
SUBFWB
SUBFWB
Read
SUBFWB
Q2
0101
3
2
1
FF
2
0
0
1
2
5
1
2
3
1
0
0
1
2
0
0
2
1
1
0
95 (5Fh). See Section 26.2.3
f
© 2006 Microchip Technology Inc.
[0,1]
[0,1]
255
; result is negative
; result is positive
; result is zero
01da
REG, 1, 0
REG, 0, 0
REG, 1, 0
f {,d {,a}}
Process
Data
Q3
dest
ffff
destination
Write to
Q4
ffff
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