PIC18F2550-I/SP Microchip Technology Inc., PIC18F2550-I/SP Datasheet - Page 258

• Manufacturer Part Number: PIC18F2550-I/SP
• Description: Microcontroller; 32 KB Flash; 2048 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2550-I/SP

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 23
• Interface: I2C/SPI/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2455/2550/4455/4550
20.3.2
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA<5>), or the Continuous Receive
Enable bit, CREN (RCSTA<4>). Data is sampled on the
RX pin on the falling edge of the clock.
If enable bit SREN is set, only a single word is received.
If enable bit CREN is set, the reception is continuous
until CREN is cleared. If both bits are set, then CREN
takes precedence.
To set up a Synchronous Master Reception:
1.
2.
3.
FIGURE 20-13:
TABLE 20-8:
DS39632C-page 256
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCON ABDOVF
SPBRGH
SPBRG
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note 1:
RC7/RX/DT/SDO
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
Name
RC6/TX/CK pin
RC6/TX/CK pin
Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud rate.
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
Ensure bits CREN and SREN are clear.
(TXCKP = 0)
(TXCKP = 1)
(Interrupt)
CREN bit
bit SREN
SREN bit
RCIF bit
RXREG
Write to
Read
Reserved in 28-pin devices; always maintain these bits clear.
EUSART SYNCHRONOUS
MASTER RECEPTION
EUSART Receive Register
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
pin
GIE/GIEH PEIE/GIEL TMR0IE
SPPIE
SPPIP
SPPIF
Q2
CSRC
SPEN
Bit 7
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
‘0’
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
(1)
(1)
(1)
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RCIDL
ADIE
ADIP
Bit 6
ADIF
RX9
TX9
bit 0
RXDTP
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 1
TXCKP
INT0IE
CREN
SYNC
TXIE
TXIP
Bit 4
TXIF
bit 2
Preliminary
ADDEN
SENDB
BRG16
SSPIF
SSPIE
SSPIP
bit 3
RBIE
Bit 3
4.
5.
6.
7.
8.
9.
10. Read the 8-bit received data by reading the
11. If any error occurred, clear the error by clearing
12. If using interrupts, ensure that the GIE and PEIE bits
If the signal from the CK pin is to be inverted, set
the TXCKP bit. If the signal from the DT pin is to
be inverted, set the RXDTP bit.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
Interrupt flag bit, RCIF, will be set when reception
is complete and an interrupt will be generated if
the enable bit, RCIE, was set.
Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
RCREG register.
bit CREN.
in the INTCON register (INTCON<7:6>) are set.
bit 4
TMR0IF
CCP1IF
CCP1IE
CCP1IP
BRGH
FERR
Bit 2
—
bit 5
TMR2IF
TMR2IE
TMR2IP
INT0IF
OERR
TRMT
WUE
Bit 1
bit 6
© 2006 Microchip Technology Inc.
TMR1IE
TMR1IP
TMR1IF
ABDEN
RX9D
TX9D
RBIF
Bit 0
bit 7
Reset Values
Q1 Q2 Q3 Q4
on page
51
54
54
54
53
53
53
53
53
53
‘0’