PIC18F2550-I/SP Microchip Technology Inc., PIC18F2550-I/SP Datasheet - Page 228

• Manufacturer Part Number: PIC18F2550-I/SP
• Description: Microcontroller; 32 KB Flash; 2048 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2550-I/SP

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 23
• Interface: I2C/SPI/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2455/2550/4455/4550
19.4.9
A Repeated Start condition occurs when the RSEN bit
(SSPCON2<1>) is programmed high and the I
module is in the Idle state. When the RSEN bit is set,
the SCL pin is asserted low. When the SCL pin is sam-
pled low, the Baud Rate Generator is loaded with the
contents of SSPADD<5:0> and begins counting. The
SDA pin is released (brought high) for one Baud Rate
Generator count (T
tor times out, if SDA is sampled high, the SCL pin will
be deasserted (brought high). When SCL is sampled
high, the Baud Rate Generator is reloaded with the
contents of SSPADD<6:0> and begins counting. SDA
and SCL must be sampled high for one T
action is then followed by assertion of the SDA pin
(SDA = 0) for one T
this, the RSEN bit (SSPCON2<1>) will be automatically
cleared and the Baud Rate Generator will not be
reloaded, leaving the SDA pin held low. As soon as a
Start condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT<3>) will be set. The SSPIF bit will
not be set until the Baud Rate Generator has timed out.
FIGURE 19-22:
DS39632C-page 226
I
START CONDITION TIMING
2
C MASTER MODE REPEATED
Falling edge of ninth clock,
BRG
BRG
REPEATED START CONDITION WAVEFORM
). When the Baud Rate Genera-
SDA
SCL
while SCL is high. Following
end of Xmit
SDA = 1,
SCL (no change).
Write to SSPCON2
occurs here.
BRG
2
C logic
. This
Preliminary
T
SDA = 1,
SCL = 1
BRG
T
BRG
Immediately following the SSPIF bit getting set, the user
may write the SSPBUF with the 7-bit address in 7-bit
mode or the default first address in 10-bit mode. After the
first eight bits are transmitted and an ACK is received,
the user may then transmit an additional eight bits of
address (10-bit mode) or eight bits of data (7-bit mode).
19.4.9.1
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
Note:
Note 1: If RSEN is programmed while any other
Sr = Repeated Start
T
BRG
2: A bus collision during the Repeated Start
Set S (SSPSTAT<3>)
At completion of Start bit,
hardware clears RSEN bit
and sets SSPIF
Because queueing of events is not
allowed, writing of the lower five bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
Write to SSPBUF occurs here
event is in progress, it will not take effect.
condition occurs if:
• SDA is sampled low when SCL goes
• SCL goes low before SDA is
WCOL Status Flag
T
from low-to-high.
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
BRG
1st bit
T
BRG
© 2006 Microchip Technology Inc.