PIC18F4580-I/P Microchip Technology Inc., PIC18F4580-I/P Datasheet - Page 147
PIC18F4580-I/P
Manufacturer Part Number
PIC18F4580-I/P
Description
40 PIN, 32 KB FLASH, 1536 RAM, 36 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F4580-IP.pdf
(402 pages)
Specifications of PIC18F4580-I/P
A/d Inputs
11-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
36
Interface
CAN/I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
40 MHz
Timers
1-8 bit, 3-16 bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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REGISTER 17-2:
2004 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE)
bit 7
WCOL: Write Collision Detect bit (Transmit mode only)
1 = The SSPBUF register is written while it is still transmitting the previous word
0 = No collision
SSPOV: Receive Overflow Indicator bit
SPI Slave mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case
0 = No overflow
SSPEN: Synchronous Serial Port Enable bit
1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled
0011 = SPI Master mode, clock = TMR2 output/2
0010 = SPI Master mode, clock = F
0001 = SPI Master mode, clock = F
0000 = SPI Master mode, clock = F
Legend:
R = Readable bit
-n = Value at POR
WCOL
R/W-0
Note:
Note:
Note:
(must be cleared in software)
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode.The user
must read the SSPBUF even if only transmitting data to avoid setting overflow (must be
cleared in software).
In Master mode, the overflow bit is not set since each new reception (and
transmission) is initiated by writing to the SSPBUF register.
When enabled, these pins must be properly configured as input or output.
Bit combinations not specifically listed here are either reserved or implemented in
I
2
SSPOV
C mode only.
R/W-0
W = Writable bit
‘1’ = Bit is set
SSPEN
R/W-0
OSC
OSC
OSC
R/W-0
CKP
/64
/16
/4
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SSPM3
R/W-0
SSPM2
R/W-0
PIC18FXX8
x = Bit is unknown
SSPM1
R/W-0
DS41159D-page 145
SSPM0
R/W-0
bit 0
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