PIC18F4580-I/P Microchip Technology Inc., PIC18F4580-I/P Datasheet - Page 301
PIC18F4580-I/P
Manufacturer Part Number
PIC18F4580-I/P
Description
40 PIN, 32 KB FLASH, 1536 RAM, 36 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F4580-IP.pdf
(402 pages)
Specifications of PIC18F4580-I/P
A/d Inputs
11-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
36
Interface
CAN/I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
40 MHz
Timers
1-8 bit, 3-16 bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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CPFSGT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
2004 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
PC
W
If REG
If REG
Q1
Q1
Q1
PC
PC
register ‘f’
operation
operation
operation
Compare f with W, Skip if f > W
[ label ] CPFSGT
0
a
(f)
skip if (f) > (W)
(unsigned comparison)
None
Compares the contents of data memory
location ‘f’ to the contents of the W by
performing an unsigned subtraction.
If the contents of ‘f’ are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
1
1(2)
Note:
HERE
NGREATER
GREATER
Read
0110
No
No
No
Q2
Q2
Q2
f
[0,1]
=
=
=
=
W),
255
3 cycles if skip and followed
by a 2-word instruction.
Address (HERE)
?
W;
Address (GREATER)
W;
Address (NGREATER)
010a
operation
operation
operation
CPFSGT REG
:
:
Process
Data
No
No
No
Q3
Q3
Q3
f [,a]
ffff
operation
operation
operation
operation
No
No
No
No
Q4
Q4
Q4
ffff
CPFSLT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
PC
W
If REG
PC
If REG
PC
Q1
Q1
Q1
register ‘f’
operation
operation
operation
Compare f with W, Skip if f < W
[ label ] CPFSLT
0
a
(f) – W),
skip if (f) < (W)
(unsigned comparison)
None
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If the contents of ‘f’ are less than the
contents of W, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected. If ‘a’ is ‘1’,
the BSR will not be overridden (default).
1
1(2)
Note:
HERE
NLESS
LESS
Read
0110
No
No
No
Q2
Q2
Q2
f
=
=
<
=
=
[0,1]
PIC18FXX8
255
3 cycles if skip and followed
by a 2-word instruction.
Address (HERE)
?
W;
Address (LESS)
W;
Address (NLESS)
CPFSLT REG
:
:
000a
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
DS41159D-page 299
f [,a]
ffff
operation
operation
operation
operation
No
No
No
No
Q4
Q4
Q4
ffff
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