PIC18F4580-I/P Microchip Technology Inc., PIC18F4580-I/P Datasheet - Page 62
PIC18F4580-I/P
Manufacturer Part Number
PIC18F4580-I/P
Description
40 PIN, 32 KB FLASH, 1536 RAM, 36 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F4580-IP.pdf
(402 pages)
Specifications of PIC18F4580-I/P
A/d Inputs
11-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
36
Interface
CAN/I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
40 MHz
Timers
1-8 bit, 3-16 bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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REGISTER 5-1:
DS41159D-page 60
PIC18FXX8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
EECON1: EEPROM CONTROL REGISTER 1
bit 7
EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access program Flash memory
0 = Access data EEPROM memory
CFGS: Flash Program/Data EE or Configuration Select bit
1 = Access Configuration registers
0 = Access program Flash or data EEPROM memory
Unimplemented: Read as ‘0’
FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
0 = Perform write only
WRERR: Write Error Flag bit
1 = A write operation is prematurely terminated
0 = The write operation completed
WREN: Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the EEPROM or Flash memory
WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle
0 = Write cycle is complete
RD: Read Control bit
1 = Initiates an EEPROM read
0 = Does not initiate an EEPROM read
Legend:
R = Readable bit
-n = Value at POR
EEPGD
R/W-x
Note:
(reset by hardware)
(any MCLR or any WDT Reset during self-timed programming in normal operation)
(The operation is self-timed and the bit is cleared by hardware once write is complete. The
WR bit can only be set (not cleared) in software.)
(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)
in software. RD bit cannot be set when EEPGD = 1.)
When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows
tracing of the error condition.
R/W-x
CFGS
W = Writable bit
‘1’ = Bit is set
U-0
—
R/W-0
FREE
S = Settable bit
‘0’ = Bit is cleared
WRERR
R/W-x
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
WREN
R/W-0
2004 Microchip Technology Inc.
R/S-0
WR
R/S-0
RD
bit 0
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