PIC18F4580-I/P Microchip Technology Inc., PIC18F4580-I/P Datasheet - Page 187

• Manufacturer Part Number: PIC18F4580-I/P
• Description: 40 PIN, 32 KB FLASH, 1536 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4580-I/P

• A/d Inputs: 11-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: CAN/I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 3-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

18.1
The BRG supports both the Asynchronous and
Synchronous modes of the USART. It is a dedicated
8-bit Baud Rate Generator. The SPBRG register
controls the period of a free running, 8-bit timer. In
Asynchronous mode, bit BRGH (TXSTA register) also
controls the baud rate. In Synchronous mode, bit
BRGH is ignored. Table 18-1 shows the formula for
computation of the baud rate for different USART
modes which only apply in Master mode (internal
clock).
Given the desired baud rate and F
integer value for the SPBRG register can be calculated
using the formula in Table 18-1. From this, the error in
baud rate can be determined.
EXAMPLE 18-1:
TABLE 18-1:
TABLE 18-2:
 2004 Microchip Technology Inc.
Desired Baud Rate
Solving for X:
Calculated Baud Rate
Error
Legend: X = value in SPBRG (0 to 255)
TXSTA
RCSTA
SPBRG
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
Name
SYNC
0
1
USART Baud Rate Generator
(BRG)
Baud Rate Generator Register
CSRC
SPEN
Bit 7
(Asynchronous) Baud Rate = F
(Synchronous) Baud Rate = F
BAUD RATE FORMULA
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
CALCULATING BAUD RATE ERROR
Bit 6
RX9
TX9
X = ((F
X = ((16000000/9600)/64) – 1
X = [25.042] = 25
= F
= 16000000/(64 (25 + 1))
= 9615
= (Calculated Baud Rate – Desired Baud Rate)
= (9615 – 9600)/9600
= 0.16%
BRGH = 0 (Low Speed)
SREN
TXEN
OSC
Bit 5
OSC
/(64 (X + 1))
OSC
/Desired Baud Rate)/64) – 1
Desired Baud Rate
, the nearest
SYNC
CREN
Bit 4
OSC
OSC
/(4 (X + 1))
/(64 (X + 1))
ADDEN
Bit 3
—
BRGH
FERR
Bit 2
Example 18-1 shows the calculation of the baud rate
error for the following conditions:
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the F
baud rate error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before
outputting the new baud rate.
18.1.1
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
OERR
TRMT
Bit 1
Baud Rate = F
NA
SAMPLING
F
Desired Baud Rate = 9600
BRGH = 0
SYNC = 0
OSC
OSC
TX9D
RX9D
Bit 0
/(16(X + 1)) equation can reduce the
= 16 MHz
BRGH = 1 (High Speed)
0000 -010
0000 000x
0000 0000
POR, BOR
PIC18FXX8
Value on
OSC
/(16 (X + 1))
DS41159D-page 185
0000 -010
0000 000u
0000 0000
Value on
all other
Resets