PIC18F45K22-I/P Microchip Technology Inc., PIC18F45K22-I/P Datasheet - Page 198
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PIC18F45K22-I/P
Manufacturer Part Number
PIC18F45K22-I/P
Description
40 PDIP .600in TUBE, 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F45K22-IP.pdf
(496 pages)
Specifications of PIC18F45K22-I/P
A/d Inputs
28-Channel, 10-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
35
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
3-8-bit, 4-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC18(L)F2X/4XK22
14.4.6
In Single Output mode, PWM steering allows any of the
PWM pins to be the modulated signal. Additionally, the
same PWM signal can be simultaneously available on
multiple pins.
Once
(CCPxM<3:2> = 11
CCPxCON register), the user firmware can bring out
the same PWM signal to one, two, three or four output
pins by setting the appropriate Steering Enable bits
(STRxA, STRxB, STRxC and/or STRxD) of the
PSTRxCON register, as shown in
While the PWM Steering mode is active, CCPxM<1:0>
bits of the CCPxCON register select the PWM output
polarity for the PxD, PxC, PxB and PxA pins.
The PWM auto-shutdown operation also applies to
PWM Steering mode as described in
“Enhanced PWM Auto-shutdown
shutdown event will only affect pins that have PWM
outputs enabled.
DS41412D-page 198
Note:
the
PWM STEERING MODE
The associated TRIS bits must be set to
output (‘0’) to enable the pin output driver
in order to see the PWM signal on the pin.
Single
and
Output
PxM<1:0> = 00
mode
Table
Mode”. An auto-
Section 14.4.3
14-13.
is
selected
of
Preliminary
the
FIGURE 14-18:
14.4.6.1
The STRxSYNC bit of the PSTRxCON register gives
the user two selections of when the steering event will
happen. When the STRxSYNC bit is ‘0’, the steering
event will happen at the end of the instruction that
writes to the PSTRxCON register. In this case, the
output signal at the PxA, PxB, PxC and PxD pins may
be an incomplete PWM waveform. This operation is
useful when the user firmware needs to immediately
remove a PWM signal from the pin.
When the STRxSYNC bit is ‘1’, the effective steering
update will happen at the beginning of the next PWM
period. In this case, steering on/off the PWM output will
always produce a complete PWM waveform.
Figures
of the PWM steering depending on the STRxSYNC
setting.
Note 1: Port outputs are configured as shown when
PORT Data
PORT Data
PORT Data
PORT Data
PxA Signal
CCPxM1
CCPxM0
CCPxM1
CCPxM0
2: Single PWM output requires setting at least
14-19
STRxC
STRxD
STRxA
STRxB
the CCPxCON register bits PxM<1:0> = 00
and CCPxM<3:2> = 11.
one of the STRx bits.
Steering Synchronization
and
14-20
SIMPLIFIED STEERING
BLOCK DIAGRAM
2010 Microchip Technology Inc.
illustrate the timing diagrams
1
0
1
0
1
0
1
0
TRIS
TRIS
TRIS
TRIS
PxB pin
PxA pin
PxC pin
PxD pin
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