PIC18F45K22-I/P Microchip Technology Inc., PIC18F45K22-I/P Datasheet - Page 53
PIC18F45K22-I/P
Manufacturer Part Number
PIC18F45K22-I/P
Description
40 PDIP .600in TUBE, 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F45K22-IP.pdf
(496 pages)
Specifications of PIC18F45K22-I/P
A/d Inputs
28-Channel, 10-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
35
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
3-8-bit, 4-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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FIGURE 3-7:
3.4.3
In RC_IDLE mode, the CPU is disabled but the periph-
erals continue to be clocked from the internal oscillator
block from the HFINTOSC multiplexer output. This
mode allows for controllable power conservation during
Idle periods.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then set
the SCS1 bit and execute SLEEP. It is recommended
that SCS0 also be cleared, although its value is
ignored, to maintain software compatibility with future
devices. The HFINTOSC multiplexer may be used to
select a higher clock frequency by modifying the IRCF
bits before executing the SLEEP instruction. When the
clock source is switched to the HFINTOSC multiplexer,
the primary oscillator is shut down and the OSTS bit is
cleared.
If the IRCF bits are set to any non-zero value, or either
the INTSRC or MFIOSEL bits are set, the HFINTOSC
output is enabled. Either the HFIOFS or the MFIOFS
bits become set, after the HFINTOSC output stabilizes
after an interval of T
HFIOFS and MFIOFS bits, see
2010 Microchip Technology Inc.
CPU Clock
Peripheral
Program
Counter
OSC1
Clock
RC_IDLE MODE
Q1
TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
IOBST
. For information on the
Wake Event
Table
3-2.
T
CSD
Preliminary
PC
Clocks
HFINTOSC source stabilizes. The HFIOFS and
MFIOFS bits will remain set if the IRCF bits were
previously set at a non-zero value or if INTSRC was set
before the SLEEP instruction was executed and the
HFINTOSC source was already stable. If the IRCF bits
and INTSRC are all clear, the HFINTOSC output will
not be enabled, the HFIOFS and MFIOFS bits will
remain clear and there will be no indication of the
current clock source.
When a wake event occurs, the peripherals continue to
be clocked from the HFINTOSC multiplexer output.
After a delay of T
CPU begins executing code being clocked by the
HFINTOSC multiplexer. The IDLEN and SCS bits are
not affected by the wake-up. The LFINTOSC source
will continue to run if either the WDT or the Fail-Safe
Clock Monitor is enabled.
PIC18(L)F2X/4XK22
to
the
Q2
CSD
peripherals
following the wake event, the
Q3
continue
DS41412D-page 53
while
Q4
the
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