PIC18F45K22-I/P Microchip Technology Inc., PIC18F45K22-I/P Datasheet - Page 362

• Manufacturer Part Number: PIC18F45K22-I/P
• Description: 40 PDIP .600in TUBE, 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F45K22-I/P

• A/d Inputs: 28-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 35
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 3-8-bit, 4-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18(L)F2X/4XK22
24.3
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC
The user program memory is divided into three or five
blocks, depending on the device. One of these is a
Boot Block of 0.5K or 2K bytes, depending on the
device. The remainder of the memory is divided into
individual blocks on binary boundaries.
FIGURE 24-2:
TABLE 24-5:
DS41412D-page 362
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
Legend: Shaded bits are unimplemented.
Note
®
microcontroller devices.
File Name
(PIC18(L)FX3K22)
(2000h-1FFFFFh)
1: Available on PIC18(L)FX5K22 and PIC18(L)FX6K22 devices only.
2: In user mode, this bit is read-only and cannot be self-programmed.
Program Verification and
Code Protection
Unimplemented
(1000h-1FFFh)
(000h-1FFh)
(200h-FFFh)
Boot Block
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
Read ‘0’s
8 Kbytes
Block 0
Block 1
CONFIGURATION REGISTERS ASSOCIATED WITH CODE PROTECTION
CODE-PROTECTED PROGRAM MEMORY FOR PIC18(L)F2X/4XK22
WRTD
Bit 7
CPD
(PIC18(L)FX4K22)
—
—
—
—
(4000h-1FFFFFh)
Unimplemented
(2000h-3FFFh)
(800h-1FFFh)
(000h-7FFh)
16 Kbytes
Boot Block
Read ‘0’s
Block 0
Block 1
MEMORY SIZE/DEVICE
EBTRB
WRTB
Bit 6
CPB
—
—
—
WRTC
(PIC18(L)FX5K22)
Bit 5
(8000h-1FFFFFh)
Preliminary
—
—
—
—
—
Unimplemented
(2000h-3FFFh)
(4000h-5FFFh)
(6000h-7FFFh)
(800h-1FFFh)
(000h-7FFh)
Boot Block
32 Kbytes
Read ‘0’s
(2)
Block 0
Block 1
Block 2
Block 3
Bit 4
—
—
—
—
—
—
Each of the blocks has three code protection bits asso-
ciated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 24-2
for 8, 16 and 32-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in
(10000h-1FFFFFh)
(PIC18(L)FX6K22)
EBTR3
WRT3
(C000h-FFFFh)
Unimplemented
(8000h-BFFFh)
(4000h-7FFFh)
CP3
(800h-3FFFh)
(000h-7FFh)
Bit 3
Boot Block
64 Kbytes
—
—
—
Read ‘0’s
shows the program memory organization
Block 0
Block 1
Block 2
Block 3
(1)
(1)
(1)
EBTR2
WRT2
CP2
Bit 2
 2010 Microchip Technology Inc.
—
—
—
(1)
(1)
(1)
Block Code Protection
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
(Unimplemented
Memory Space)
Controlled By:
EBTR1
WRT1
Bit 1
CP1
—
—
—
Table
EBTR0
24-5.
WRT0
Bit 0
CP0
—
—
—