PIC18F45K22-I/P Microchip Technology Inc., PIC18F45K22-I/P Datasheet - Page 42
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PIC18F45K22-I/P
Manufacturer Part Number
PIC18F45K22-I/P
Description
40 PDIP .600in TUBE, 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F45K22-IP.pdf
(496 pages)
Specifications of PIC18F45K22-I/P
A/d Inputs
28-Channel, 10-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
35
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
3-8-bit, 4-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC18(L)F2X/4XK22
2.9.3
When switching between one oscillator and another,
the new oscillator may not be operating which saves
power (see
delay after the SCS<1:0> bits of the OSCCON register
are modified before the frequency change takes place.
The OSTS and IOFS bits of the OSCCON register will
reflect the current active status of the external and
HFINTOSC oscillators. The timing of a frequency
selection is as follows:
1.
2.
3.
4.
5.
6.
7.
See
If the HFINTOSC is the source of both the old and new
frequency, there is no start-up delay before the new
frequency is active. This is because the old and new
frequencies are derived from the HFINTOSC via the
postscaler and multiplexer.
Start-up
Section 27.0 “Electrical
Specifications (Oscillator Module).
DS41412D-page 42
SCS<1:0> bits of the OSCCON register are mod-
ified.
The old clock continues to operate until the new
clock is ready.
Clock switch circuitry waits for two consecutive
rising edges of the old clock after the new clock
ready signal goes true.
The system clock is held low starting at the next
falling edge of the old clock.
Clock switch circuitry waits for an additional two
rising edges of the new clock.
On the next falling edge of the new clock the low
hold on the system clock is released and new
clock is switched in as the system clock.
Clock switch is complete.
Figure 2-1
delay
CLOCK SWITCH TIMING
Figure
for more details.
2-9). If this is the case, there is a
specifications
Characteristics”, under AC
are
located
Preliminary
in
2.10
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external
oscillator start-up and code execution. In applications
that make heavy use of the Sleep mode, Two-Speed
Start-up will remove the external oscillator start-up
time from the time spent awake and can reduce the
overall power consumption of the device.
This mode allows the application to wake-up from
Sleep, perform a few instructions using the HFINTOSC
as the clock source and go back to Sleep without
waiting for the primary oscillator to become stable.
When the oscillator module is configured for LP, XT or
HS modes, the Oscillator Start-up Timer (OST) is
enabled (see
(OST)”). The OST will suspend program execution until
1024 oscillations are counted. Two-Speed Start-up
mode minimizes the delay in code execution by
operating from the internal oscillator as the OST is
counting. When the OST count reaches 1024 and the
OSTS bit of the OSCCON register is set, program
execution switches to the external oscillator.
2.10.1
Two-Speed Start-up mode is enabled when all of the
following settings are configured as noted:
• Two-Speed Start-up mode is enabled when the
• SCS<1:0> (of the OSCCON register) = 00.
• FOSC<2:0> bits of the CONFIG1H Configuration
Two-Speed Start-up mode becomes active after:
• Power-on Reset (POR) and, if enabled, after
• Wake-up from Sleep.
Note:
IESO of the CONFIG1H Configuration register is
set.
register are configured for LP, XT or HS mode.
Power-up Timer (PWRT) has expired, or
Two-Speed Clock Start-up Mode
Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit of the OSCCON register to
remain clear.
TWO-SPEED START-UP MODE
CONFIGURATION
Section 2.4.1 “Oscillator Start-up Timer
2010 Microchip Technology Inc.
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