PIC18F45K22-I/P Microchip Technology Inc., PIC18F45K22-I/P Datasheet - Page 295
PIC18F45K22-I/P
Manufacturer Part Number
PIC18F45K22-I/P
Description
40 PDIP .600in TUBE, 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F45K22-IP.pdf
(496 pages)
Specifications of PIC18F45K22-I/P
A/d Inputs
28-Channel, 10-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
35
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
3-8-bit, 4-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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17.2
17.2.1
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the GO/
DONE bit of the ADCON0 register to a ‘1’ will, depend-
ing on the ACQT bits of the ADCON2 register, either
immediately start the Analog-to-Digital conversion or
start an acquisition delay followed by the Analog-to-
Digital conversion.
FIGURE 17-3:
FIGURE 17-4:
2010 Microchip Technology Inc.
(Holding capacitor continues
acquiring input)
Set GO bit
1
T
CY
Set GO bit
T
ADC Operation
Holding capacitor is disconnected from analog input (typically 100 ns)
ACQT
Acquisition
Automatic
- T
STARTING A CONVERSION
2
Time
AD
Conversion starts
Cycles
T
AD
3
1 T
A/D CONVERSION T
A/D CONVERSION T
AD
b9
4
2 T
Conversion starts
(Holding capacitor is disconnected from analog input)
AD
b8
1
3 T
AD
b9
2
b7
4 T
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
AD
b8
3
b6
AD
AD
5 T
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
CYCLES (A
CYCLES (A
Preliminary
AD
b5
b7
4
6 T
T
AD
b4
5
b6
AD
7 T
Cycles
Figure 17-3
after the GO bit has been set and the ACQT<2:0> bits
are cleared. A conversion is started after the following
instruction to allow entry into SLEEP mode before the
conversion begins.
Figure 17-4
after the GO bit has been set and the ACQT<2:0> bits
are set to ‘010’ which selects a 4 T
before the conversion starts.
CQT
AD
CQT
b3
b5
Note:
6
PIC18(L)F2X/4XK22
8
<2:0> = 000, T
<2:0> = 010, T
T
AD
b4
b2
7
9 T
The GO/DONE bit should not be set in the
same instruction that turns on the ADC.
Refer to
sion
shows the operation of the A/D converter
shows the operation of the A/D converter
AD
b3
8
b1
Procedure”.
10
T
Section 17.2.10 “A/D Conver-
AD
ACQ
b0
b2
9
ACQ
11
2 T
= 0)
10
= 4 T
Discharge
b1
AD
AD
AD
b0
DS41412D-page 295
11
)
acquisition time
2 T
Discharge
AD
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