DSPIC30F2020-30I/SP Microchip Technology Inc., DSPIC30F2020-30I/SP Datasheet - Page 118

• Manufacturer Part Number: DSPIC30F2020-30I/SP
• Description: DSP, 16-Bit, 12KB Flash, 512 RAM, 21 I/O, SDIP-28
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F2020-30I/SP

• A/d Inputs: 8-Channels, 10-Bit
• Comparators: 4
• Cpu Speed: 30 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/UART
• Ios: 21
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 28-pin SPDIP
• Programmable Memory: 12K Bytes
• Ram Size: 512 Bytes
• Timers: 3-16-bit, 1-32-bit
• Voltage, Range: 3-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

dsPIC30F1010/202X
REGISTER 12-11: IOCONx: PWM I/O CONTROL REGISTER
DS70178C-page 116
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11-10
bit 9
bit 8
bit 7-6
bit 5-4
bit 3-2
bit 1
bit 0
R/W-0
PENH
R/W-0
OVRDAT<1:0>
PENH: PWMH Output Pin Ownership bit
1 = PWM module controls PWMxH pin
0 = GPIO module controls PWMxH pin
PENL: PWML Output Pin Ownership bit
1 = PWM module controls PWMxL pin
0 = GPIO module controls PWMxL pin
POLH: PWMH Output Pin Polarity bit
1 = PWMxH pin is low active
0 = PWMxH pin is high active
POLL: PWML Output Pin Polarity bit
1 = PWMxL pin is low active
0 = PWMxL pin is high active
PMOD<1:0>: PWM #x I/O Pin Mode bits
00 = PWM I/O pin pair is in the Complementary Output mode
01 = PWM I/O pin pair is in the Independent Output mode
10 = PWM I/O pin pair is in the Push-Pull Output mode
11 = Reserved
OVRENH:
1 = OVRDAT<1> provides data for output on PWMxH pin
0 = PWM generator provides data for PWMxH pin
OVRENL: Override Enable for PWMxL Pin bit
1 = OVRDAT<0> provides data for output on PWMxL pin
0 = PWM generator provides data for PWMxL pin
OVRDAT<1:0>: Data for PWMxH,L Pins if Override is Enabled bits
If OVERENH = 1 then OVRDAT<1> provides data for PWMxH
If OVERENL = 1 then OVRDAT<0> provides data for PWMxL
FLTDAT<1:0>: Data for PWMxH,L Pins if FLTMODE is Enabled bits
If Fault active, then FLTDAT<1> provides data for PWMxH
If Fault active, then FLTDAT<0> provides data for PWMxL
CLDAT<1:0>: Data for PWMxH,L Pins if CLMODE is Enabled bits
If current limit active, then CLDAT<1> provides data for PWMxH
If current limit active, then CLDAT<0> provides data for PWMxL
Unimplemented: Read as ‘0’
OSYNC: Output Override Synchronization bit
1 = Output overrides via the OVRDAT<1:0> bits are synchronized to the PWM time base
0 = Output overrides via the OVDDAT<1:0> bits occur on next clock boundary
R/W-0
R/W-0
PENL
Override Enable for PWMxH Pin bit
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
POLH
FLTDAT<1:0>
R/W-0
R/W-0
POLL
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
R/W-0
CLDAT<1:0>
PMOD<1:0>
R/W-0
R/W-0
© 2006 Microchip Technology Inc.
x = Bit is unknown
OVRENH
R/W-0
U-0
—
OVRENL
OSYNC
R/W-0
R/W-0
bit 8
bit 0