DSPIC30F4013-20E/P Microchip Technology Inc., DSPIC30F4013-20E/P Datasheet - Page 198

• Manufacturer Part Number: DSPIC30F4013-20E/P
• Description: 16 BIT MCU/DSP 40LD 20MIPS 48 KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F4013-20E/P

• A/d Inputs: 13-Channels, 12-Bit
• Comparators: 4
• Cpu Speed: 30 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 30
• Interface: CAN, I2C/SPI/UART, USART
• Ios: 30
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 40-pin PDIP
• Programmable Memory: 48K Bytes
• Ram Size: 2K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

dsPIC30F2011/2012/3012/3013
Reset Sequence.................................................................. 65
Reset Sources
Reset Timing Characteristics ............................................ 161
Reset Timing Requirements.............................................. 161
Run-Time Self-Programming (RTSP) ................................. 47
S
Simple Capture Event Mode ............................................... 81
Simple OC/PWM Mode Timing Requirements.................. 167
Simple Output Compare Match Mode................................. 86
Simple PWM Mode ............................................................. 86
Software Simulator (MPLAB SIM)..................................... 142
Software Stack Pointer, Frame Pointer............................... 18
SPI Module.......................................................................... 89
Status Bits, Their Significance and the Initialization
Status Bits, Their Significance and the Initialization
Status Register.................................................................... 18
Symbols Used in Opcode Descriptions............................. 134
System Integration
T
Table Instruction Operation Summary ................................ 47
Temperature and Voltage Specifications
Timer 2/3 Module ................................................................ 75
Timer1 Module .................................................................... 71
DS70139D-page 196
Power-on Reset (POR) ............................................. 119
Power-up Timer (PWRT) .......................................... 119
Reset Sources ............................................................ 65
Brown-out Reset (BOR) .............................................. 65
Illegal Instruction Trap................................................. 65
Trap Lockout ............................................................... 65
Uninitialized W Register Trap ..................................... 65
Watchdog Time-out..................................................... 65
Buffer Operation.......................................................... 82
Hall Sensor Mode ....................................................... 82
Prescaler ..................................................................... 81
Timer2 and Timer3 Selection Mode ............................ 82
Input Pin Fault Protection............................................ 86
Period.......................................................................... 87
CALL Stack Frame...................................................... 37
Framed SPI Support ................................................... 90
Operating Function Description .................................. 89
Operation During CPU Idle Mode ............................... 91
Operation During CPU Sleep Mode ............................ 91
SDOx Disable ............................................................. 90
Slave Select Synchronization ..................................... 91
SPI1 Register Map ...................................................... 92
Timing Characteristics
Timing Requirements
Word and Byte Communication .................................. 90
Condition for RCON Register, Case 1 ...................... 128
Condition for RCON Register, Case 2 ...................... 128
Register Map............................................................. 132
AC ............................................................................. 155
DC ............................................................................. 145
16-bit Asynchronous Counter Mode ........................... 71
16-bit Synchronous Counter Mode ............................. 71
16-bit Timer Mode ....................................................... 71
Gate Operation ........................................................... 72
Master Mode (CKE = 0) .................................... 168
Master Mode (CKE = 1) .................................... 169
Slave Mode (CKE = 1) .............................. 170, 171
Master Mode (CKE = 0) .................................... 168
Master Mode (CKE = 1) .................................... 169
Slave Mode (CKE = 0) ...................................... 170
Slave Mode (CKE = 1) ...................................... 172
Timer2 and Timer3 Selection Mode.................................... 86
Timer2/3 Module
Timing Characteristics
Timing Diagrams
Timing Diagrams and Specifications
Timing Diagrams.See Timing Characteristics
Timing Requirements
Interrupt ...................................................................... 72
Operation During Sleep Mode .................................... 72
Prescaler .................................................................... 72
Real-Time Clock ......................................................... 72
Register Map .............................................................. 74
16-bit Timer Mode....................................................... 75
32-bit Synchronous Counter Mode ............................. 75
32-bit Timer Mode....................................................... 75
ADC Event Trigger...................................................... 78
Gate Operation ........................................................... 78
Interrupt ...................................................................... 78
Operation During Sleep Mode .................................... 78
Register Map .............................................................. 79
Timer Prescaler .......................................................... 78
A/D Conversion
Bandgap Start-up Time............................................. 162
CAN Module I/O........................................................ 177
CLKOUT and I/O ...................................................... 160
External Clock........................................................... 155
I
I
Input Capture (CAPX)............................................... 165
OC/PWM Module...................................................... 167
Oscillator Start-up Timer........................................... 161
Output Compare Module .......................................... 166
Power-up Timer ........................................................ 161
Reset ........................................................................ 161
SPI Module
Type A, B and C Timer External Clock ..................... 163
Watchdog Timer ....................................................... 161
PWM Output Timing ................................................... 87
Time-out Sequence on Power-up (MCLR Not
Time-out Sequence on Power-up (MCLR Not
Time-out Sequence on Power-up (MCLR
DC Characteristics - Internal RC Accuracy............... 158
A/D Conversion
Bandgap Start-up Time............................................. 162
Brown-out Reset ....................................................... 161
CAN Module I/O........................................................ 177
CLKOUT and I/O ...................................................... 160
External Clock........................................................... 156
I
I
2
2
2
2
C Bus Data
C Bus Start/Stop Bits
C Bus Data (Master Mode) .................................... 174
C Bus Data (Slave Mode) ...................................... 175
Interrupts ............................................................ 73
Oscillator Operation............................................ 73
Low-speed (ASAM = 0, SSRC = 000) .............. 180
Master Mode..................................................... 173
Slave Mode....................................................... 175
Master Mode..................................................... 173
Slave Mode....................................................... 175
Master Mode (CKE = 0).................................... 168
Master Mode (CKE = 1).................................... 169
Slave Mode (CKE = 0)...................................... 170
Slave Mode (CKE = 1)...................................... 171
Tied to V
Tied to V
Tied to V
Low-speed ........................................................ 181
DD
DD
DD
), Case 1 ........................................ 126
), Case 2 ........................................ 126
)...................................................... 126
© 2006 Microchip Technology Inc.