DSPIC30F4013-20E/P Microchip Technology Inc., DSPIC30F4013-20E/P Datasheet - Page 87

• Manufacturer Part Number: DSPIC30F4013-20E/P
• Description: 16 BIT MCU/DSP 40LD 20MIPS 48 KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F4013-20E/P

• A/d Inputs: 13-Channels, 12-Bit
• Comparators: 4
• Cpu Speed: 30 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 30
• Interface: CAN, I2C/SPI/UART, USART
• Ios: 30
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 40-pin PDIP
• Programmable Memory: 48K Bytes
• Ram Size: 2K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

12.0
This section describes the output compare module and
associated operational modes. The features provided
by this module are useful in applications requiring oper-
ational modes, such as:
• Generation of Variable Width Output Pulses
• Power Factor Correction
Figure 12-1 depicts a block diagram of the output
compare module.
FIGURE 12-1:
© 2006 Microchip Technology Inc.
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “ dsPIC30F Family Reference
Manual” (DS70046).
Note:
OUTPUT COMPARE MODULE
From GP
Timer Module
TMR2<15:0
Where ‘x’ is shown, reference is made to the registers associated with the respective output compare
channel (1 or 2).
0
OUTPUT COMPARE MODE BLOCK DIAGRAM
Comparator
OCxRS
OCxR
TMR3<15:0>
dsPIC30F2011/2012/3012/3013
1
OCTSEL
T2P2_MATCH
0
The key operational features of the output compare
module include:
• Timer2 and Timer3 Selection mode
• Simple Output Compare Match mode
• Dual Output Compare Match mode
• Simple PWM mode
• Output Compare During Sleep and Idle modes
• Interrupt on Output Compare/PWM Event
These operating modes are determined by setting the
appropriate bits in the 16-bit OC1CON and OC2CON
registers. The dsPIC30F2011/2012/3012/3013 devices
have 2 compare channels.
OCxRS and OCxR in Figure 12-1 represent the Dual
Compare registers. In the Dual Compare mode, the
OCxR register is used for the first compare and OCxRS
is used for the second compare.
T3P3_MATCH
Mode Select
OCM<2:0>
1
Output
3
Logic
Set Flag bit
OCxIF
R
S
Q
Output
Enable
(for x = 1, 2, 3 or 4)
OCFA
DS70139D-page 85
OCx