DS26518GN+ Maxim Integrated Products, DS26518GN+ Datasheet - Page 211
![IC TXRX T1/E1/J1 8PORT 256-CSBGA](/photos/6/50/65053/256-csbga_21-0315_sml.jpg)
DS26518GN+
Manufacturer Part Number
DS26518GN+
Description
IC TXRX T1/E1/J1 8PORT 256-CSBGA
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Specifications of DS26518GN+
Number Of Drivers/receivers
8/8
Protocol
T1/E1/J1
Voltage - Supply
3.135 V ~ 3.465 V
Mounting Type
Surface Mount
Package / Case
256-CSBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: Bits 6 and 7 are used for fractional backplane support. See Section 9.8.5.
Bit 7: Transmit Channel Data Format (TDATFMT)
Bit 6: Transmit Gapped Clock Enable (TGCLKEN)
Bit 4: Transmit Slip Zone Select (TSZS). This bit determines the minimum distance allowed between the elastic
store read and write pointers before forcing a controlled slip. This bit is only applies during T1 to E1 or E1 to T1
conversion applications.
Bit 3: Transmit Elastic Store Align (TESALGN). Setting this bit from a zero to a one will force the transmit elastic
store’s write/read pointers to a minimum separation of half a frame. No action will be taken if the pointer separation
is already greater or equal to half a frame. If pointer separation is less than half a frame, the command will be
executed and the data will be disrupted. Should be toggled after TSYSCLKn has been applied and is stable. Must
be cleared and set again for a subsequent align.
Bit 2: Transmit Elastic Store Reset (TESR). Setting this bit from a zero to a one will force the read pointer into
the same frame that the write pointer is exiting, minimizing the delay through the elastic store. If this command
should place the pointers within the slip zone (see bit 4), then an immediate slip will occur and the pointers will
move back to opposite frames. Should be toggled after TSYSCLKn has been applied and is stable. Do not leave
this bit set high.
Bit 1: Transmit Elastic Store Minimum Delay Mode (TESMDM)
Bit 0: Transmit Elastic Store Enable (TESE)
0 = 64kbps (data contained in all 8 bits).
1 = 56kbps (data contained in 7 out of the 8 bits).
0 = TCHCLK functions normally.
1 = Enable gapped bit clock output on TCHCLKn.
0 = Force a slip at 9 bytes or less of separation (used for clustered blank channels).
1 = Force a slip at 2 bytes or less of separation (used for distributed blank channels).
0 = Elastic stores operate at full two-frame depth.
1 = Elastic stores operate at 32-bit depth.
0 = Elastic store is bypassed.
1 = Elastic store is enabled.
TDATFMT
7
0
TGCLKEN
TESCR
Transmit Elastic Store Control Register
185h + (200h x (n - 1)) : where n = 1 to 8
6
0
—
5
0
211 of 286
TSZS
4
0
TESALGN
3
0
DS26518 8-Port T1/E1/J1 Transceiver
TESR
2
0
TESMDM
1
0
TESE
0
0
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