DS26518GN+ Maxim Integrated Products, DS26518GN+ Datasheet - Page 28

• Manufacturer Part Number: DS26518GN+
• Description: IC TXRX T1/E1/J1 8PORT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26518GN+

• Number Of Drivers/receivers: 8/8
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.
9.1
Microprocessor control of the DS26518 is accomplished through the 28 hardware pins of the microprocessor port.
The 8-bit parallel data bus can be configured for Intel or Motorola modes of operation with the bus type select
(BTS) pin. When the BTS pin is a logic 0, bus timing is in Intel mode, as shown in
When the BTS pin is a logic 1, bus timing is in Motorola mode, as shown in
address space is mapped through the use of 13 address lines, A[12:0]. Multiplexed mode is not supported on the
processor interface.
The chip-select bar (CSB) pin must be brought to a logic-low level to gain read and write access to the
microprocessor port. With Intel timing selected, the read-data bar (RDB) and write-read bar (WRB) pins are used to
indicate read and write operations and latch data through the interface. With Motorola timing selected, the read-
write bar (RWB) pin is used to indicate read and write operations while the data-strobe bar (DSB) pin is used to
latch data through the interface.
The interrupt output pin (INTB) is an open-drain output that asserts a logic-low level upon a number of software
maskable interrupt conditions. This pin is normally connected to the microprocessor interrupt input.
9.1.1 SPI Serial Port Mode
The external processor bus can be configured to operate in SPI serial bus mode. See Section
timing diagrams.
When SPI_SEL = 1, SPI bus mode is implemented using four signals: clock (SPI_SCLK), master out-slave in data
(SPI_MOSI), master in-slave out data (SPI_MISO), and chip select (CSB). Clock polarity and phase can be set by
the D[7]/SPI_CPOL and D[6]/SPI_CPHA pins.
The order of the address and data bits in the serial stream is selectable using the D[5]/SPI_SWAP pin. The R/W bit
is always first and B bit is always last in the initial control word and are not effected by the D[5]/SPI_SWAP pin
setting.
SPI mode is not recommended for HDLC operations because of the bandwidth constraints of SPI.
9.1.2 SPI Functional Timing Diagrams
Note: The transmit and receive order of the address and data bits are selected by the D[5]/SPI_SWAP pin. The
R/W (read/write) MSB bit and B (burst) LSB bit position is not affected by the D[5]/SPI_SWAP pin setting.
9.1.2.1 SPI Transmission Format and CPHA Polarity
When SPI_CPHA = 0, CSB may be deasserted between accesses. An access is defined as one or two control
bytes followed by a data byte. CSB cannot be deasserted between the control bytes, or between the last control
byte and the data byte. When SPI_CPHA = 0, CSB may also remain asserted between accesses. If it remains
asserted and the BURST bit is set, no additional control bytes are expected after the first control byte(s) and data
are transferred. If the BURST bit is set, the address will be incremented for each additional byte of data transferred
until CSB is deasserted. If CSB remains asserted and the BURST bit is not set, a control byte(s) is expected
following the data byte, and the address for the next access will be received from that. Anytime CSB is deasserted,
the BURST access is terminated.
When SPI_CPHA = 1, CSB may remain asserted for more than one access without being toggled high and then
low again between accesses. If the BURST bit is set, the address should increment and no additional control bytes
are expected. If the BURST bit is not set, each data byte will be followed by the control byte(s) for the next access.
Additionally, CSB may also be deasserted between accesses when SPI_CPHA = 1. In the case, any BURST
access is terminated and the next byte received when CSB is reasserted will be a control byte.
The following diagrams describe the functionality of the SPI port for the four combinations of SPI_CPOL and
SPI_CPHA. They indicate the clock edge that samples the data and the level of the clock during no-transfer events
(high or low). Since the SPI port of the DS26518 acts as a slave device, the master device provides the clock. The
FUNCTIONAL DESCRIPTION
Processor Interface
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DS26518 8-Port T1/E1/J1 Transceiver
Figure 13-4
Figure 13-2
and
Figure
9.1.2
and
Figure
for detailed
13-5. The
13-3.