PIC18F4550-I/ML Microchip Technology Inc., PIC18F4550-I/ML Datasheet - Page 144

• Manufacturer Part Number: PIC18F4550-I/ML
• Description: 44 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4550-I/ML

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 34
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2450/4450
TABLE 14-4:
TABLE 14-5:
DS39760A-page 142
Legend: (E) = Even transaction buffer, (O) = Odd transaction buffer
BDnSTAT
BDnCNT
BDnADRL
BDnADRH
Note 1:
Endpoint
Name
2:
3:
4:
10
12
13
14
15
11
0
1
2
3
4
5
6
7
8
9
(1)
(1)
(1)
(1)
For buffer descriptor registers, n may have a value of 0 to 63. For the sake of brevity, all 64 registers are
shown as one generic prototype. All registers have indeterminate Reset values (xxxx xxxx).
Bits 5 through 2 of the BDnSTAT register are used by the SIE to return PID3:PID0 values once the register
is turned over to the SIE (UOWN bit is set). Once the registers have been under SIE control, the values
written for DTSEN and BSTALL are no longer valid.
Prior to turning the buffer descriptor over to the SIE (UOWN bit is cleared), bits 3 and 2 of the BDnSTAT
register are used to configure the DTSEN and BSTALL settings.
This bit is ignored unless DTSEN = 1.
Byte Count
Buffer Address Low
Buffer Address High
ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT
BUFFERING MODES
SUMMARY OF USB BUFFER DESCRIPTOR TABLE REGISTERS
UOWN
Bit 7
Out
10
12
14
16
18
20
22
24
26
28
30
(No Ping-Pong)
0
2
4
6
8
Mode 0
DTS
Bit 6
(4)
11
13
15
17
19
21
23
25
27
29
31
In
1
3
5
7
9
PID3
Advance Information
Bit 5
(2)
0 (E), 1 (O)
(Ping-Pong on EP0 OUT)
Out
11
13
15
17
19
21
23
25
27
29
31
BDs Assigned to Endpoint
3
5
7
9
PID2
Bit 4
Mode 1
(2)
DTSEN
PID1
10
12
14
16
18
20
22
24
26
28
30
32
In
2
4
6
8
Bit 3
(2)
(3)
BSTALL
12 (E), 13 (O)
16 (E), 17 (O)
20 (E), 21 (O)
24 (E), 25 (O)
28 (E), 29 (O)
32 (E), 33 (O)
36 (E), 37 (O)
40 (E), 41 (O)
44 (E), 45 (O)
48 (E), 49 (O)
52 (E), 53 (O)
56 (E), 57 (O)
60 (E), 61 (O)
PID0
0 (E), 1 (O)
4 (E), 5 (O)
8 (E), 9 (O)
Bit 2
(Ping-Pong on all EPs)
Out
© 2006 Microchip Technology Inc.
(2)
(3)
Mode 2
Bit 1
BC9
14 (E), 15 (O)
18 (E), 19 (O)
22 (E), 23 (O)
26 (E), 27 (O)
34 (E), 35 (O)
38 (E), 39 (O)
42 (E), 43 (O)
46 (E), 47 (O)
50 (E), 51 (O)
54 (E), 55 (O)
58 (E), 59 (O)
62 (E), 63 (O)
10 (E), 11 (O)
30 (E), 31 (O)
2 (E), 3 (O)
6 (E), 7 (O)
In
Bit 0
BC8