PIC18F4550-I/ML Microchip Technology Inc., PIC18F4550-I/ML Datasheet - Page 155
PIC18F4550-I/ML
Manufacturer Part Number
PIC18F4550-I/ML
Description
44 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F4550-IML.pdf
(320 pages)
Specifications of PIC18F4550-I/ML
A/d Inputs
13-Channel, 10-Bit
Comparators
2
Cpu Speed
12 MIPS
Eeprom Memory
256 Bytes
Input Output
34
Interface
I2C/SPI/UART/USART/USB
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin QFN
Programmable Memory
32K Bytes
Ram Size
2K Bytes
Speed
48 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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15.0
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial
Communications Interface or SCI.) The USART can be
configured as a full-duplex asynchronous system that
can communicate with peripheral devices, such as
CRT terminals and personal computers. It can also be
configured as a half-duplex synchronous system that
can communicate with peripheral devices, such as A/D
or D/A integrated circuits, serial EEPROMs and so on.
The Enhanced Universal Synchronous Receiver
Transmitter (EUSART) module implements additional
features, including Automatic Baud Rate Detection
(ABD) and calibration, automatic wake-up on Sync
Break reception and 12-bit Break character transmit.
These features make it ideally suited for use in Local
Interconnect Network bus (LIN bus) systems.
The EUSART can be configured in the following
modes:
• Asynchronous (full-duplex) with:
• Synchronous – Master (half-duplex) with
• Synchronous – Slave (half-duplex) with selectable
© 2006 Microchip Technology Inc.
- Auto-wake-up on character reception
- Auto-baud calibration
- 12-bit Break character transmission
selectable clock polarity
clock polarity
ENHANCED UNIVERSAL
SYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
Advance Information
The pins of the Enhanced USART are multiplexed with
PORTC. In order to configure RC6/TX/CK and RC7/RX/
DT as an EUSART:
• bit SPEN (RCSTA<7>) must be set (= 1)
• bit TRISC<7> must be set (= 1)
• bit TRISC<6> must be cleared (= 0) for
The operation of the Enhanced USART module is
controlled through three registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
• Baud Rate Control (BAUDCON)
These are detailed on the following pages in
Register 15-1,
respectively.
Asynchronous and Synchronous Master modes
or set (= 1) for Synchronous Slave mode
Note:
PIC18F2450/4450
The EUSART control will automatically
reconfigure the pin from input to output as
needed.
Register 15-2
and
DS39760A-page 153
Register 15-3,
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