PIC18F4550-I/ML Microchip Technology Inc., PIC18F4550-I/ML Datasheet - Page 34

• Manufacturer Part Number: PIC18F4550-I/ML
• Description: 44 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4550-I/ML

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 34
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2450/4450
2.5
When PRI_IDLE mode is selected, the designated
primary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. Unless the USB
module is enabled, the OSC1 pin (and OSC2 pin if
used by the oscillator) will stop oscillating.
In
SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1.
In internal oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator provides the device clock source.
The 31 kHz INTRC output can be used directly to
provide the clock and may be enabled to support various
special features regardless of the power-managed
mode (see Section 18.2 “Watchdog Timer (WDT)”,
Section 18.3 “Two-Speed Start-up” and Section 18.4
“Fail-Safe Clock Monitor” for more information on
WDT, Fail-Safe Clock Monitor and Two-Speed Start-up).
Regardless of the Run or Idle mode selected, the USB
clock source will continue to operate. If the device is
operating from a crystal or resonator-based oscillator,
that oscillator will continue to clock the USB module.
The core and all other modules will switch to the new
clock source.
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Sleep mode should never be invoked while the USB
module is operating and connected. The only exception
is when the device has been issued a “Suspend” com-
mand over the USB. Once the module has suspended
operation and shifted to a low-power state, the
microcontroller may be safely put into Sleep mode.
TABLE 2-4:
DS39760A-page 32
INTCKO
INTIO
ECIO, ECPIO
EC
XT and HS
Note:
secondary
Oscillator Mode
Effects of Power-Managed Modes
on the Various Clock Sources
See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.
clock
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
modes
Floating, pulled by external clock
Floating, pulled by external clock
Floating, pulled by external clock
Floating, pulled by external clock
Feedback inverter disabled at quiescent
voltage level
(SEC_RUN
Advance Information
OSC1 Pin
and
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a Real-
Time Clock. Other features may be operating that do
not require a device clock source (i.e., PSP, INTn pins
and others). Peripherals that may add significant
current consumption are listed in Section 21.2 “DC
Characteristics: Power-Down and Supply Current”.
2.6
Power-up delays are controlled by two timers, so that no
external Reset circuitry is required for most applications.
The delays ensure that the device is kept in Reset until
the device power supply is stable under normal circum-
stances and the primary clock is operating and stable.
For additional information on power-up delays, see
Section 4.5 “Device Reset Timers”.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 21-10). It is enabled by clearing (= 0) the
PWRTEN Configuration bit.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (XT and HS modes). The
OST does this by counting 1024 oscillator cycles
before allowing the oscillator to clock the device.
When the HSPLL Oscillator mode is selected, the
device is kept in Reset for an additional 2 ms following
the HS mode OST delay, so the PLL can lock to the
incoming clock frequency.
There is a delay of interval, T
Table 21-10), following POR, while the controller
becomes ready to execute instructions. This delay runs
concurrently with any other delays. This may be the
only delay that occurs when any of the EC or internal
oscillator modes are used as the primary clock source.
Power-up Delays
At logic low (clock/4 output)
Configured as PORTA, bit 6
Configured as PORTA, bit 6
At logic low (clock/4 output)
Feedback inverter disabled at quiescent
voltage level
© 2006 Microchip Technology Inc.
OSC2 Pin
CSD
(parameter 38,