PIC18F4550-I/ML Microchip Technology Inc., PIC18F4550-I/ML Datasheet - Page 205

• Manufacturer Part Number: PIC18F4550-I/ML
• Description: 44 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4550-I/ML

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 34
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

18.3
The Two-Speed Start-up feature helps to minimize the
latency period, from oscillator start-up to code
execution, by allowing the microcontroller to use the
INTRC oscillator as a clock source until the primary
clock source is available. It is enabled by setting the
IESO Configuration bit.
Two-Speed Start-up should be enabled only if the
primary oscillator mode is XT, HS, XTPLL or HSPLL
(Crystal-based modes). Other sources do not require
an OST start-up delay; for these, Two-Speed Start-up
should be disabled.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the
internal oscillator as the clock source, following the
time-out of the Power-up Timer after a Power-on Reset
is enabled. This allows almost immediate code
execution while the primary oscillator starts and the
OST is running. Once the OST times out, the device
automatically switches to PRI_RUN mode.
Because the OSCCON register is cleared on Reset
events, the INTRC clock is used directly at its base
frequency.
FIGURE 18-2:
© 2006 Microchip Technology Inc.
Two-Speed Start-up
Note 1:
CPU Clock
PLL Clock
Peripheral
Program
Counter
INTRC
Output
OSC1
Clock
T
Wake from Interrupt Event
OST
TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC TO HSPLL)
= 1024 T
PC
OSC
; T
Q1
PLL
T
OST
= 2 ms (approx). These intervals are not shown to scale.
(1)
Q2
Advance Information
PC + 2
T
PLL
OSTS bit Set
Q3
(1)
Q4
In all other power-managed modes, Two-Speed Start-up
is not used. The device will be clocked by the currently
selected clock source until the primary clock source
becomes available. The setting of the IESO bit is
ignored.
18.3.1
While using the INTRC oscillator in Two-Speed Start-up,
the device still obeys the normal command sequences
for entering power-managed modes, including serial
SLEEP instructions (refer to Section 3.1.4 “Multiple
Sleep Commands”). In practice, this means that user
code can change the SCS1:SCS0 bit settings or issue
SLEEP instructions before the OST times out. This would
allow an application to briefly wake-up, perform routine
“housekeeping” tasks and return to Sleep before the
device starts to operate from the primary oscillator.
User code can also check if the primary clock source is
currently providing the device clocking by checking the
status of the OSTS bit (OSCCON<3>). If the bit is set,
the primary oscillator is providing the clock. Otherwise,
the internal oscillator is providing the clock during
wake-up from Reset or Sleep mode.
Q1
1
Transition
2
Clock
PIC18F2450/4450
n-1 n
SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
PC + 4
Q2
Q3 Q4
Q1
PC + 6
DS39760A-page 203
Q2
Q3