PIC18F4550-I/ML Microchip Technology Inc., PIC18F4550-I/ML Datasheet - Page 192

• Manufacturer Part Number: PIC18F4550-I/ML
• Description: 44 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4550-I/ML

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 34
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2450/4450
18.1
The Configuration bits can be programmed (read as
‘0’) or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh), which
can only be accessed using table reads and table writes.
TABLE 18-1:
DS39760A-page 190
300000h
300001h
300002h
300003h
300005h
300006h
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
3FFFFEh DEVID1
3FFFFFh DEVID2
Legend:
Note 1:
File Name
2:
Configuration Bits
CONFIG1L
CONFIG1H
CONFIG2L
CONFIG2H
CONFIG3H MCLRE
CONFIG4L
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as ‘0’.
See Register 18-13 and Register 18-14 for device ID values. DEVID registers are read-only and cannot be programmed
by the user.
Available only on PIC18F4450 devices in 44-pin TQFP packages. Always leave this bit clear in all other devices.
CONFIGURATION BITS AND DEVICE IDs
DEBUG
DEV10
DEV2
IESO
Bit 7
—
—
—
—
—
—
—
—
—
FCMEN
EBTRB
XINST
WRTB
DEV1
DEV9
Bit 6
CPB
—
—
—
—
—
—
—
VREGEN
ICPRT
USBDIV CPUDIV1 CPUDIV0 PLLDIV2
WRTC
DEV0
DEV8
Bit 5
Advance Information
—
—
—
—
—
—
—
—
(2)
WDTPS3 WDTPS2 WDTPS1 WDTPS0
BORV1
REV4
DEV7
Bit 4
—
—
—
—
—
—
—
—
—
FOSC3
BORV0
BBSIZ
REV3
DEV6
Programming the Configuration registers is done in a
manner similar to programming the Flash memory. The
WR bit in the EECON1 register starts a self-timed write
to the Configuration register. In normal operation mode,
a TBLWT instruction, with the TBLPTR pointing to the
Configuration register, sets up the address and the
data for the Configuration register write. Setting the WR
bit starts a long write to the Configuration register. The
Configuration registers are written a byte at a time. To
write or erase a configuration cell, a TBLWT instruction
can write a ‘1’ or a ‘0’ into the cell. For additional details
on Flash programming, refer to Section 6.5 “Writing
to Flash Program Memory”.
Bit 3
—
—
—
—
—
—
—
LPT1OSC PBADEN
BOREN1 BOREN0 PWRTEN
FOSC2
REV2
DEV5
Bit 2
LVP
—
—
—
—
—
—
PLLDIV1
FOSC1
EBTR1
WRT1
REV1
DEV4
Bit 1
CP1
—
—
—
—
© 2006 Microchip Technology Inc.
STVREN
PLLDIV0
WDTEN
FOSC0
EBTR0
WRT0
REV0
DEV3
Bit 0
CP0
—
—
—
—
Unprogrammed
--00 0000
00-- 0101
--01 1111
---1 1111
1--- -01-
100- 01-1
---- --11
-1-- ----
---- --11
-11- ----
---- --11
-1-- ----
xxxx xxxx
0001 0010
Default/
Value
(1)
(1)