PIC18F46K80-I/ML Microchip Technology Inc., PIC18F46K80-I/ML Datasheet - Page 178

• Manufacturer Part Number: PIC18F46K80-I/ML
• Description: 44 QFN 8X8X0.9MM TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F46K80-I/ML

• A/d Inputs: 11-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 35
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin QFN
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F66K80 FAMILY
REGISTER 11-1:
REGISTER 11-2:
DS39977C-page 178
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3-1
bit 0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
RDPU
WPUB7
R/W-0
R/W-1
2:
(1)
Unimplemented on 28-pin devices.
Unimplemented on 40-pin devices.
RDPU: PORTD Pull-up Enable bit
1 = PORTD pull-up resistors are enabled by individual port latch values
0 = All PORTD pull-up resistors are disabled
REPU: PORTE Pull-up Enable bit
1 = PORTE pull-up resistors are enabled by individual port latch values
0 = All PORTE pull-up resistors are disabled
RFPU: PORTF Pull-up Enable bit
1 = PORTF pull-up resistors are enabled by individual port latch values
0 = All PORTF pull-up resistors are disabled
RGPU: PORTG Pull-up Enable bit
1 = PORTG pull-up resistors are enabled by individual port latch values
0 = All PORTG pull-up resistors are disabled
Unimplemented: Read as ‘ 0 ’
CTMUDS: CTMU Comparator Data Select bit
1 = External comparator (with output on pin CTDIN) is used for CTMU compares
0 = Internal comparator (CMP2) is used for CTMU compares
WPUB<7:0>: Weak Pull-Up Enable Register bits
1 = Pull-up enabled on corresponding PORTB pin when RBPU = 0 and the pin is an input
0 = Pull-up disabled on corresponding PORTB pin
REPU
WPUB6
R/W-0
R/W-1
PADCFG1: PAD CONFIGURATION REGISTER
WPUB: WEAK PULL-UP PORTB ENABLE REGISTER
(1)
W = Writable bit
W = Writable bit
‘1’ = Bit is set
‘1’ = Bit is set
RFPU
WPUB5
R/W-0
R/W-1
(2)
RGPU
WPUB4
R/W-0
R/W-1
(2)
(1)
(1)
Preliminary
(2)
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
WPUB3
R/W-1
U-0
—
WPUB2
R/W-1
U-0
—
 2011 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
WPUB1
R/W-1
U-0
—
CTMUDS
WPUB0
R/W-0
R/W-1
bit 0
bit 0