PIC18F46K80-I/ML Microchip Technology Inc., PIC18F46K80-I/ML Datasheet - Page 287

• Manufacturer Part Number: PIC18F46K80-I/ML
• Description: 44 QFN 8X8X0.9MM TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F46K80-I/ML

• A/d Inputs: 11-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 35
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin QFN
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

20.4.6
In half-bridge applications, where all power switches
are modulated at the PWM frequency, the power
switches normally require more time to turn off than to
turn on. If both the upper and lower power switches are
switched at the same time (one turned on and the other
turned off), both switches may be on for a short period
until one switch completely turns off. During this brief
interval, a very high current (shoot-through current) will
flow through both power switches, shorting the bridge
supply.
shoot-through current from flowing during switching,
turning on either of the power switches is normally
delayed to allow the other switch to completely turn off.
In Half-Bridge mode, a digitally programmable
dead-band delay is available to avoid shoot-through
current from destroying the bridge power switches. The
delay occurs at the signal transition from the non-active
state to the active state. For an illustration, see
Figure
ECCP1DEL register
period in terms of microcontroller instruction cycles
(T
FIGURE 20-15:
 2011 Microchip Technology Inc.
CY
Standard Half-Bridge Circuit (“Push-Pull”)
or 4 T
20-14. The lower seven bits of the associated
To
OSC
PROGRAMMABLE DEAD-BAND
DELAY MODE
).
avoid
EXAMPLE OF HALF-BRIDGE APPLICATIONS
(Register
this
potentially
20-4) set the delay
P1A
P1B
destructive
Preliminary
FET
Driver
FET
Driver
PIC18F66K80 FAMILY
FIGURE 20-14:
P1A
P1B
td = Dead-Band Delay
Note 1: At this time, the TMR2 register is equal to the
(2)
(2)
V+
V-
2: Output signals are shown as active-high.
(1)
td
Pulse Width
PR2 register.
Load
Period
td
EXAMPLE OF
HALF-BRIDGE PWM
OUTPUT
+
V
-
+
V
-
(1)
DS39977C-page 287
Period
(1)