PIC18F46K80-I/ML Microchip Technology Inc., PIC18F46K80-I/ML Datasheet - Page 213

• Manufacturer Part Number: PIC18F46K80-I/ML
• Description: 44 QFN 8X8X0.9MM TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F46K80-I/ML

• A/d Inputs: 11-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 35
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin QFN
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

13.3
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable.
Its value is set by the PSA and T0PS<2:0> bits
(T0CON<3:0>),
assignment and prescale ratio.
Clearing the PSA bit assigns the prescaler to the
Timer0 module. When it is assigned, prescale values
from 1:2 through 1:256, in power-of-two increments,
are selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (for example, CLRF TMR0 ,
MOVWF TMR0 , BSF TMR0 ) clear the prescaler count.
TABLE 13-1:
 2011 Microchip Technology Inc.
TMR0L
TMR0H
INTCON
T0CON
PMD1
Legend: — = unimplemented, read as ‘ 0 ’. Shaded cells are not used by Timer0.
Note:
Name
Prescaler
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
Timer0 Register Low Byte
Timer0 Register High Byte
GIE/GIEH
TMR0ON
PSPMD
which
REGISTERS ASSOCIATED WITH TIMER0
Bit 7
determine
PEIE/GIEL
CTMUMD
T08BIT
Bit 6
the
TMR0IE
ADCMD
T0CS
prescaler
Bit 5
Preliminary
TMR4MD
INT0IE
T0SE
Bit 4
PIC18F66K80 FAMILY
13.3.1
The prescaler assignment is fully under software
control and can be changed “on-the-fly” during program
execution.
13.4
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h in 8-bit mode, or
from FFFFh to 0000h in 16-bit mode. This overflow sets
the TMR0IF flag bit. The interrupt can be masked by
clearing the TMR0IE bit (INTCON<5>). Before re-
enabling the interrupt, the TMR0IF bit must be cleared
in software by the Interrupt Service Routine (ISR).
Since Timer0 is shutdown in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
TMR3MD
RBIE
Bit 3
PSA
Timer0 Interrupt
SWITCHING PRESCALER
ASSIGNMENT
TMR2MD
TMR0IF
T0PS2
Bit 2
TMR1MD
INT0IF
T0PS1
Bit 1
DS39977C-page 213
TMR0MD
T0PS0
RBIF
Bit 0