PIC12F683-I/MD Microchip Technology Inc., PIC12F683-I/MD Datasheet - Page 29

• Manufacturer Part Number: PIC12F683-I/MD
• Description: 8 PIN, 3.5KB FLASH, 128 RAM, 6 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC12F683-I/MD

• A/d Inputs: 4-Channel, 10-Bit
• Comparators: 1
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Frequency: 20 MHz
• Input Output: 6
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 8-Pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Serial Interface: None
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

3.7
The Fail-Safe Clock Monitor (FSCM) is designed to
allow the device to continue to operate in the event of
an oscillator failure. The FSCM can detect oscillator
failure at any point after the device has exited a Reset
or Sleep condition and the Oscillator Start-up Timer
(OST) has expired.
FIGURE 3-8:
The FSCM function is enabled by setting the FCMEN
bit in the Configuration Word register (CONFIG). It is
applicable to all external clock options (LP, XT, HS, EC,
RC or IO modes).
In the event of an external clock failure, the FSCM will
set the OSFIF bit (PIR1<2>) and generate an oscillator
fail interrupt if the OSFIE bit (PIE1<2>) is set. The
device will then switch the system clock to the internal
oscillator. The system clock will continue to come from
the internal oscillator unless the external clock recovers
and the Fail-Safe condition is exited.
The frequency of the internal oscillator will depend
upon
(OSCCON<6:4>).
condition, the OSTS bit (OSCCON<3>) is automati-
cally cleared to reflect that the internal oscillator is
FIGURE 3-9:
 2004 Microchip Technology Inc.
LFINTOSC
Oscillator
Sample Clock
Note:
the
CM Output
Fail-Safe Clock Monitor
Primary
Clock
OSCFIF
System
Output
Clock
value
(Q)
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
÷ 64
Upon
contained
FSCM BLOCK DIAGRAM
FSCM TIMING DIAGRAM
entering
Detector
Clock
Fail
in
CM Test
the
the
IRCF
Clock
Failure
Detected
Fail-Safe
Preliminary
bits
active and the WDT is cleared. The SCS bit
(OSCCON<0>) is not updated. Enabling FSCM does
not affect the LTS bit.
The FSCM sample clock is generated by dividing the
INTRC clock by 64. This will allow enough time
between FSCM sample clocks for a system clock edge
to occur. Figure 3-8 shows the FSCM block diagram.
On the rising edge of the sample clock, the monitoring
latch (CM = 0) will be cleared. On a falling edge of the
primary system clock, the monitoring latch will be set
(CM = 1). In the event that a falling edge of the sample
clock occurs and the monitoring latch is not set, a clock
failure has been detected. The assigned internal oscil-
lator is enabled when FSCM is enabled, as reflected by
the IRCF.
3.7.1
The Fail-Safe condition is cleared after a Reset, the
execution of a SLEEP instruction, or a modification of
the SCS bit. While in Fail-Safe condition, the
PIC12F683 uses the internal oscillator as the system
clock source. The IRCF bits (OSCCON<6:4>) can be
modified to adjust the internal oscillator frequency
without exiting the Fail-Safe condition.
The Fail-Safe condition must be cleared before the
OSFIF flag can be cleared.
CM Test
Note:
Note:
Oscillator
Failure
Two-Speed
enabled when the Fail-Safe Clock Monitor
mode is enabled.
Primary clocks with a frequency ~488 Hz
will be considered failed by the FSCM. A
slow starting oscillator can cause an
FSCM interrupt.
FAIL-SAFE CONDITION CLEARING
Detected
Start-up
PIC12F683
Failure
CM Test
is
DS41211B-page 27
automatically