PIC12F683-I/MD Microchip Technology Inc., PIC12F683-I/MD Datasheet - Page 57

• Manufacturer Part Number: PIC12F683-I/MD
• Description: 8 PIN, 3.5KB FLASH, 128 RAM, 6 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC12F683-I/MD

• A/d Inputs: 4-Channel, 10-Bit
• Comparators: 1
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Frequency: 20 MHz
• Input Output: 6
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 8-Pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Serial Interface: None
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

9.0
The
conversion of an analog input signal to a 10-bit binary
representation of that signal. The PIC12F683 has four
analog inputs, multiplexed into one sample and hold
FIGURE 9-1:
9.1
There are two registers available to control the
functionality of the A/D module:
1.
2.
9.1.1
The ANS<3:0> bits (ANSEL<3:0>) and the TRISIO bits
control the operation of the A/D port pins. Set the cor-
responding TRISIO bits to set the pin output driver to its
high-impedance state. Likewise, set the corresponding
ANSEL bit to disable the digital input buffer.
9.1.2
There are four analog channels on the PIC12F683,
AN0 through AN3. The CHS bits (ADCON0<3:2>)
control which channel is connected to the sample and
hold circuit.
 2004 Microchip Technology Inc.
Note:
ADCON0 (Register 9-1)
ANSEL (Register 9-2)
Analog-to-Digital
ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
A/D Configuration and Operation
ANALOG PORT PINS
Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.
CHANNEL SELECTION
GP1/AN1/V
A/D BLOCK DIAGRAM
GP0/AN0
GP2/AN2
GP4/AN3
converter
REF
CHS<1:0>
(A/D)
V
REF
allows
Preliminary
V
DD
GO/DONE
VCFG = 0
VCFG = 1
ADON
circuit. The output of the sample and hold is connected
to the input of the converter. The converter generates a
binary result via successive approximation and stores
the result in a 10-bit register. The voltage reference
used in the conversion is software selectable to either
V
shows the block diagram of the A/D on the PIC12F683.
9.1.3
There are two options for the voltage reference to the
A/D converter: either V
applied to V
controls the voltage reference selection. If VCFG is set,
then the voltage on the V
otherwise, V
9.1.4
The A/D conversion cycle requires 11 T
of the conversion clock is software selectable via the
ADCS bits (ANSEL<6:4>). There are seven possible
clock options:
• F
• F
• F
• F
• F
• F
• F
For correct conversion, the A/D conversion clock
(1/T
1.6 s. Table 9-1 shows a few T
selected frequencies.
V
DD
SS
OSC
OSC
OSC
OSC
OSC
OSC
RC
AD
or a voltage applied by the V
A/D
) must be selected to ensure a minimum T
(dedicated internal oscillator)
/2
/4
/8
/16
/32
/64
ADFM
VOLTAGE REFERENCE
CONVERSION CLOCK
REF
DD
is the reference.
is used. The VCFG bit (ADCON0<6>)
ADRESH ADRESL
DD
is used, or an analog voltage
PIC12F683
10
10
REF
pin is the reference;
AD
REF
DS41211B-page 55
calculations for
AD
pin. Figure 9-1
. The source
AD
of