PIC12F683-I/MD Microchip Technology Inc., PIC12F683-I/MD Datasheet - Page 78

• Manufacturer Part Number: PIC12F683-I/MD
• Description: 8 PIN, 3.5KB FLASH, 128 RAM, 6 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC12F683-I/MD

• A/d Inputs: 4-Channel, 10-Bit
• Comparators: 1
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Frequency: 20 MHz
• Input Output: 6
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 8-Pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Serial Interface: None
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC12F683
12.1
The configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’) to select various
device configurations as shown in Register 12-1.
These bits are mapped in program memory location
2007h.
REGISTER 12-1:
DS41211B-page 76
bit 13
bit 13-12
bit 11
bit 10
bit 9-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
—
Configuration Bits
—
Legend:
R = Readable bit
- n = Value at POR
Unimplemented: Read as ‘1’
FCMEN: Fail-Safe Clock Monitor Enabled bit
1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
IESO: Internal External Switchover bit
1 = Internal External Switchover mode is enabled
0 = Internal External Switchover mode is disabled
BODEN<1:0>: Brown-out Detect Selection bits
11 = BOD enabled
10 = BOD enabled during operation and disabled in Sleep
01 = BOD controlled by SBODEN bit (PCON<4>)
00 = BOD disabled
CPD: Data Code Protection bit
1 = Data memory code protection is disabled
0 = Data memory code protection is enabled
CP: Code Protection bit
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
MCLRE: GP3/MCLR pin function select bit
1 = GP3/MCLR pin function is MCLR
0 = GP3/MCLR pin function is digital input, MCLR internally tied to V
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled and can be enabled by SWDTEN bit (WDTCON<0>)
FOSC<2:0>: Oscillator Selection bits
111 = RC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN
110 = RCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN
101 = INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN
100 = INTOSCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN
011 = EC: I/O function on RA4/OSC2/CLKOUT pin, CLKIN on RA5/OSC1/CLKIN
010 = HS oscillator: High-speed crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN
001 = XT oscillator: Crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN
000 = LP oscillator: Low-power crystal on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN
Note 1: Enabling Brown-out Detect does not automatically enable Power-up Timer.
FCMEN
2: The entire data EEPROM will be erased when the code protection is turned off.
3: The entire program memory will be erased when the code protection is turned off. When MCLR is asserted
CONFIG – CONFIGURATION WORD (ADDRESS: 2007h)
in INTOSC or RC mode, the internal clock oscillator is disabled.
IESO
BODEN1 BODEN0
(3)
(2)
W = Writable bit
‘1’ = Bit is set
(4)
Preliminary
CPD
(1)
CP
Note:
MCLRE PWRTE
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
DD
program memory space. It belongs to the
special
(2000h-3FFFh), which can be accessed
only
“PIC12F6XX/16F6XX Memory Program-
ming Specification” (DS41204) for more
information.
Address 2007h is
during
configuration
WDTE
 2004 Microchip Technology Inc.
x = Bit is unknown
FOSC2 FOSC1 FOSC0
programming.
beyond the user
memory
space
See
bit 0