PIC18F46K80-I/P Microchip Technology Inc., PIC18F46K80-I/P Datasheet - Page 518
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC18F46K80-I/P
Manufacturer Part Number
PIC18F46K80-I/P
Description
40 PDIP .600IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F46K80-IPT.pdf
(628 pages)
Specifications of PIC18F46K80-I/P
A/d Inputs
11-Channel, 12-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
1K Bytes
Input Output
35
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin PDIP
Programmable Memory
64K Bytes
Ram Size
3.6K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
2-8-bit, 3-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F46K80-I/PT
Manufacturer:
BROADCOM
Quantity:
101
Company:
Part Number:
PIC18F46K80-I/PT
Manufacturer:
Microchip Technology
Quantity:
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Part Number:
PIC18F46K80-I/PT
Manufacturer:
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Quantity:
20 000
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PIC18F66K80 FAMILY
RETFIE
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39977C-page 518
Q Cycle Activity:
After Interrupt
operation
Decode
PC
W
BSR
STATUS
GIE/GIEH, PEIE/GIEL
No
Q1
operation
operation
Return from Interrupt
RETFIE {s}
s [0,1]
(TOS) PC,
1 GIE/GIEH or PEIE/GIEL;
if s = 1 ,
(WS) W,
(STATUSS) STATUS,
(BSRS) BSR,
PCLATU, PCLATH are unchanged
GIE/GIEH, PEIE/GIEL.
Return from interrupt. Stack is popped
and Top-of-Stack (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high or low-priority
global interrupt enable bit. If ‘s’ = 1 , the
contents of the shadow registers WS,
STATUSS and BSRS are loaded into
their corresponding registers W,
STATUS and BSR. If ‘s’ = 0 , no update
of these registers occurs (default).
1
2
RETFIE
0000
No
No
Q2
1
0000
operation
operation
=
=
=
=
=
No
No
Q3
TOS
WS
BSRS
STATUSS
1
0001
Set GIEH or
from stack
operation
POP PC
GIEL
No
Q4
000s
Preliminary
RETLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
TABLE
Q Cycle Activity:
:
:
:
CALL TABLE ; W contains table
ADDWF PCL
RETLW k0
RETLW k1
RETLW kn
Before Instruction
After Instruction
operation
Decode
W
W
No
Q1
; offset value
; W now has
; table value
; W = offset
; Begin table
;
; End of table
=
=
operation
Return Literal to W
RETLW k
0 k 255
k W,
(TOS) PC,
PCLATU, PCLATH are unchanged
None
W is loaded with the eight-bit literal ‘k’.
The program counter is loaded from the
top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
1
2
literal ‘k’
Read
0000
No
Q2
07h
value of kn
2011 Microchip Technology Inc.
1100
operation
Process
Data
No
Q3
kkkk
from stack,
write to W
operation
POP PC
No
Q4
kkkk
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